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? 2003 microchip technology inc. ds39582b pic16f87xa data sheet 28/40/44-pin enhanced flash microcontrollers
ds39582b-page ii ? 2003 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semicondu ctor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving t he code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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pic16f87xa ds39582b-page 2 ? 2003 microchip technology inc. pin diagrams pic16f873a/876a 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /c2out v ss osc1/clki osc2/clko rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7/pgd rb6/pgc rb5 rb4 rb3/pgm rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda 28-pin pdip, soic, ssop 2 3 4 5 6 1 7 mclr /v pp ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /c2out v ss osc1/clki 15 16 17 18 19 20 21 rb3/pgm v dd v ss rb0/int rc7/rx/dt rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck 23 24 25 26 27 28 22 ra1/an1 ra0/an0 rb7/pgd rb6/pgc rb5 rb4 10 11 8 9 12 13 14 28-pin qfn pic16f873a pic16f876a rb2 rb1 rc0/t1oso/t1cki osc2/clko 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16f874a 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp rb3/pgm rb7/pgd rb6/pgc rb5 rb4 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 rc0/t1oso/t1cki osc2/clko osc1/clki v ss v ss v dd v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss /c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd v dd rb0/int rb1 rb2 44-pin qfn pic16f877a
? 2003 microchip technology inc. ds39582b-page 3 pic16f87xa pin diagrams (continued) rb7/pgd rb6/pgc rb5 rb4 rb3/pgm rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /c2out re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clki osc2/clko rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16f874a/877a 40-pin pdip 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 pic16f874a ra4/t0cki/c1out ra5/an4/ss /c2out re0/rd /an5 osc1/clki osc2/clko rc0/t1oso/t1ck1 nc re1/wr /an6 re2/cs /an7 v dd v ss rb3/pgm rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp nc rb7/pgd rb6/pgc rb5 rb4 nc nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16f874a 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp nc rb7/pgd rb6/pgc rb5 rb4 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc nc rc0/t1oso/t1cki osc2/clko osc1/clki v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss /c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3/pgm 44-pin plcc 44-pin tqfp pic16f877a pic16f877a rc7/rx/dt
pic16f87xa ds39582b-page 4 ? 2003 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................ 5 2.0 memory organization......................................................................................................... ....................................................... 15 3.0 data eeprom and flash program memory ........................................................................................ .................................... 33 4.0 i/o ports................................................................................................................... ................................................................. 41 5.0 timer0 module ............................................................................................................... ........................................................... 53 6.0 timer1 module ............................................................................................................... ........................................................... 57 7.0 timer2 module ............................................................................................................... ........................................................... 61 8.0 capture/compare/pwm modules ................................................................................................. ............................................ 63 9.0 master synchronous serial port (mssp) module................................................................................ ..................................... 71 10.0 addressable universal synchronous asynchr onous receiver transmitter (usart) ................................................ ............ 111 11.0 analog-to-digital converter (a/d) module ................................................................................... ........................................... 127 12.0 comparator module .......................................................................................................... ...................................................... 135 13.0 comparator voltage reference module ........................................................................................ ......................................... 141 14.0 special features of the cpu ................................................................................................ .................................................. 143 15.0 instruction set summary.................................................................................................... ..................................................... 159 16.0 development support ........................................................................................................ ..................................................... 167 17.0 electrical characteristics................................................................................................. ........................................................ 173 18.0 dc and ac characteristics graphs and tables ................................................................................ ..................................... 197 19.0 packaging information ...................................................................................................... ...................................................... 209 appendix a: revision history .................................................................................................... ........................................................ 219 appendix b: device differences.................................................................................................. ...................................................... 219 appendix c: conversion considerations........................................................................................... ................................................ 220 index .......................................................................................................................... ....................................................................... 221 on-line support................................................................................................................ ................................................................ 229 systems information and upgrade hot line ....................................................................................... .............................................. 229 reader response ................................................................................................................ ............................................................. 230 pic16f87xa product identification system....................................................................................... ............................................... 231 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revisi on of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at 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? 2003 microchip technology inc. ds39582b-page 5 pic16f87xa 1.0 device overview this document contains device specific information about the following devices: pic16f873a pic16f874a pic16f876a pic16f877a pic16f873a/876a devices are available only in 28-pin packages, while pic16f874a/877a devices are avail- able in 40-pin and 44-pin packages. all devices in the pic16f87xa family share common architecture with the following differences: the pic16f873a and pic16f874a have one-half of the total on-chip memory of the pic16f876a and pic16f877a the 28-pin devices have three i/o ports, while the 40/44-pin devices have five the 28-pin devices have fourteen interrupts, while the 40/44-pin devices have fifteen the 28-pin devices have five a/d input channels, while the 40/44-pin devices have eight the parallel slave port is implemented only on the 40/44-pin devices the available features are summarized in table 1-1. block diagrams of the pic16f873a/876a and pic16f874a/877a devices are provided in figure 1-1 and figure 1-2, respectively. the pinouts for these device families are listed in table 1-2 and table 1-3. additional information may be found in the picmicro ? mid-range reference manual (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip web site. the reference manual should be considered a complemen- tary document to this data sheet and is highly recom- mended reading for a better understanding of the device architecture and operation of the peripheral modules. table 1-1: pic16f87xa device features key features pic16f873a pic16f874a pic16f876a pic16f877a operating frequency dc ? 20 mhz dc ? 20 mhz dc ? 20 mhz dc ? 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) flash program memory (14-bit words) 4k 4k 8k 8k data memory (bytes) 192 192 368 368 eeprom data memory (bytes) 128 128 256 256 interrupts 14 15 14 15 i/o ports ports a, b, c ports a, b, c, d, e ports a, b, c ports a, b, c, d, e timers 3333 capture/compare/pwm modules2222 serial communications mssp, usart mssp, usart mssp, usart mssp, usart parallel communications ? psp ? psp 10-bit analog-to-digital module 5 input channels 8 input channels 5 input channels 8 input channels analog comparators 2222 instruction set 35 instructions 35 instructions 35 instructions 35 instructions packages 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin plcc 44-pin tqfp 44-pin qfn 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin plcc 44-pin tqfp 44-pin qfn
pic16f87xa ds39582b-page 6 ? 2003 microchip technology inc. figure 1-1: pic16f87 3a/876a block diagram flash 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki/c1out ra5/an4/ss /c2out rb0/int rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp1,2 synchronous 10-bit a/d timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 8 3 data eeprom rb1 rb2 rb3/pgm rb4 rb5 rb6/pgc rb7/pgd in-circuit debugger low-voltage programming comparator voltage reference device program flash data memory data eeprom pic16f873a 4k words 192 bytes 128 bytes pic16f876a 8k words 368 bytes 256 bytes program memory
? 2003 microchip technology inc. ds39582b-page 7 pic16f87xa figure 1-2: pic16f87 4a/877a block diagram 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko mclr v dd , v ss porta portb portc portd porte ra4/t0cki/c1out ra5/an4/ss /c2out rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt re0/rd /an5 re1/wr /an6 re2/cs /an7 8 8 brown-out reset note 1: higher order bits are from the status register. ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 parallel 8 3 rb0/int rb1 rb2 rb3/pgm rb4 rb5 rb6/pgc rb7/pgd in-circuit debugger low-voltage programming rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 usart ccp1,2 synchronous 10-bit a/d timer0 timer1 timer2 serial port data eeprom comparator voltage reference device program flash data memory data eeprom pic16f874a 4k words 192 bytes 128 bytes pic16f877a 8k words 368 bytes 256 bytes flash program memory slave port
pic16f87xa ds39582b-page 8 ? 2003 microchip technology inc. table 1-2: pic16f873a/876a pinout description pin name pdip, soic, ssop pin# qfn pin# i/o/p type buffer type description osc1/clki osc1 clki 9 6 i i st/cmos (3) oscillator crystal or external clock input. oscillator crystal input or ex ternal clock source input. st buffer when configured in rc mode; otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). osc2/clko osc2 clko 10 7 o o ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. mclr /v pp mclr v pp 126 i p st master clear (input) or programming voltage (output). master clear (reset) input. this pin is an active low reset to the device. programming voltage input. porta is a bidirectional i/o port. ra0/an0 ra0 an0 227 i/o i ttl digital i/o. analog input 0. ra1/an1 ra1 an1 328 i/o i ttl digital i/o. analog input 1. ra2/an2/v ref -/ cv ref ra2 an2 v ref - cv ref 41 i/o i i o ttl digital i/o. analog input 2. a/d reference voltage (low) input. comparator v ref output. ra3/an3/v ref + ra3 an3 v ref + 52 i/o i i ttl digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/c1out ra4 t0cki c1out 63 i/o i o st digital i/o ? open-drain when configured as output. timer0 external clock input. comparator 1 output. ra5/an4/ss /c2out ra5 an4 ss c2out 74 i/o i i o ttl digital i/o. analog input 4. spi slave select input. comparator 2 output. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. ds39582b-page 9 pic16f87xa portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int rb0 int 21 18 i/o i ttl/st (1) digital i/o. external interrupt. rb1 22 19 i/o ttl digital i/o. rb2 23 20 i/o ttl digital i/o. rb3/pgm rb3 pgm 24 21 i/o i ttl digital i/o. low-voltage (single-supply) icsp programming enable pin. rb4 25 22 i/o ttl digital i/o. rb5 26 23 i/o ttl digital i/o. rb6/pgc rb6 pgc 27 24 i/o i ttl/st (2) digital i/o. in-circuit debugger and icsp programming clock. rb7/pgd rb7 pgd 28 25 i/o i/o ttl/st (2) digital i/o. in-circuit debugger and icsp programming data. portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 11 8 i/o o i st digital i/o. timer1 oscillator output. timer1 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 12 9 i/o i i/o st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 13 10 i/o i/o st digital i/o. capture1 input, compare1 output, pwm1 output. rc3/sck/scl rc3 sck scl 14 11 i/o i/o i/o st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 15 12 i/o i i/o st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 16 13 i/o o st digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 14 i/o o i/o st digital i/o. usart asynchronous transmit. usart1 synchronous clock. rc7/rx/dt rc7 rx dt 18 15 i/o i i/o st digital i/o. usart asynchronous receive. usart synchronous data. v ss 8, 19 5, 6 p ? ground reference for logic and i/o pins. v dd 20 17 p ? positive supply for logic and i/o pins. table 1-2: pic16f873a/876a pinout description (continued) pin name pdip, soic, ssop pin# qfn pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16f87xa ds39582b-page 10 ? 2003 microchip technology inc. table 1-3: pic16f874a/877a pinout description pin name pdip pin# plcc pin# tqfp pin# qfn pin# i/o/p type buffer type description osc1/clki osc1 clki 13 14 30 32 i i st/cmos (4) oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). osc2/clko osc2 clko 14 15 31 33 o o ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. mclr /v pp mclr v pp 1 2 18 18 i p st master clear (input) or programming voltage (output). master clear (reset) input. this pin is an active low reset to the device. programming voltage input. porta is a bidirectional i/o port. ra0/an0 ra0 an0 2 3 19 19 i/o i ttl digital i/o. analog input 0. ra1/an1 ra1 an1 3 4 20 20 i/o i ttl digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 4 5 21 21 i/o i i o ttl digital i/o. analog input 2. a/d reference voltage (low) input. comparator v ref output. ra3/an3/v ref + ra3 an3 v ref + 5 6 22 22 i/o i i ttl digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/c1out ra4 t0cki c1out 6 7 23 23 i/o i o st digital i/o ? open-drain when configured as output. timer0 external clock input. comparator 1 output. ra5/an4/ss /c2out ra5 an4 ss c2out 7 8 24 24 i/o i i o ttl digital i/o. analog input 4. spi slave select input. comparator 2 output. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. ds39582b-page 11 pic16f87xa portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int rb0 int 33 36 8 9 i/o i ttl/st (1) digital i/o. external interrupt. rb1 34 37 9 10 i/o ttl digital i/o. rb2 35 38 10 11 i/o ttl digital i/o. rb3/pgm rb3 pgm 36 39 11 12 i/o i ttl digital i/o. low-voltage icsp programming enable pin. rb4 37 41 14 14 i/o ttl digital i/o. rb5 38 42 15 15 i/o ttl digital i/o. rb6/pgc rb6 pgc 39 43 16 16 i/o i ttl/st (2) digital i/o. in-circuit debugger and icsp programming clock. rb7/pgd rb7 pgd 40 44 17 17 i/o i/o ttl/st (2) digital i/o. in-circuit debugger and icsp programming data. table 1-3: pic16f874a/877a pinout description (continued) pin name pdip pin# plcc pin# tqfp pin# qfn pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16f87xa ds39582b-page 12 ? 2003 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 15 16 32 34 i/o o i st digital i/o. timer1 oscillator output. timer1 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 16 18 35 35 i/o i i/o st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 17 19 36 36 i/o i/o st digital i/o. capture1 input, compare1 output, pwm1 output. rc3/sck/scl rc3 sck scl 18 20 37 37 i/o i/o i/o st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 23 25 42 42 i/o i i/o st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 24 26 43 43 i/o o st digital i/o. spi data out. rc6/tx/ck rc6 tx ck 25 27 44 44 i/o o i/o st digital i/o. usart asynchronous transmit. usart1 synchronous clock. rc7/rx/dt rc7 rx dt 26 29 1 1 i/o i i/o st digital i/o. usart asynchronous receive. usart synchronous data. table 1-3: pic16f874a/877a pinout description (continued) pin name pdip pin# plcc pin# tqfp pin# qfn pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
? 2003 microchip technology inc. ds39582b-page 13 pic16f87xa portd is a bidirectional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 rd0 psp0 19 21 38 38 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 20 22 39 39 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 21 23 40 40 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 22 24 41 41 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 27 30 2 2 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd5/psp5 rd5 psp5 28 31 3 3 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd6/psp6 rd6 psp6 29 32 4 4 i/o i/o st/ttl (3) digital i/o. parallel slave port data. rd7/psp7 rd7 psp7 30 33 5 5 i/o i/o st/ttl (3) digital i/o. parallel slave port data. porte is a bidirectional i/o port. re0/rd /an5 re0 rd an5 8 9 25 25 i/o i i st/ttl (3) digital i/o. read control for parallel slave port. analog input 5. re1/wr /an6 re1 wr an6 9102626 i/o i i st/ttl (3) digital i/o. write control for parallel slave port. analog input 6. re2/cs /an7 re2 cs an7 10 11 27 27 i/o i i st/ttl (3) digital i/o. chip select control for parallel slave port. analog input 7. v ss 12, 31 13, 34 6, 29 6, 30, 31 p ? ground reference for logic and i/o pins. v dd 11, 32 12, 35 7, 28 7, 8, 28, 29 p ? positive supply for logic and i/o pins. nc ? 1, 17, 28, 40 12,13, 33, 34 13 ? ? these pins are not inter nally connected. these pins should be left unconnected. table 1-3: pic16f874a/877a pinout description (continued) pin name pdip pin# plcc pin# tqfp pin# qfn pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise.
pic16f87xa ds39582b-page 14 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 15 pic16f87xa 2.0 memory organization there are three memory blocks in each of the pic16f87xa devices. the program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. the eeprom data memory block is detailed in section 3.0 ?data eeprom and flash program memory? . additional information on device memory may be found in the picmicro ? mid-range mcu family reference manual (ds33023). figure 2-1: pic16f876a/877a program memory map and stack 2.1 program memory organization the pic16f87xa devices have a 13-bit program counter capable of addressing an 8k word x 14 bit program memory space. the pic16f876a/877a devices have 8k words x 14 bits of flash program memory, while pic16f873a/874a devices have 4k words x 14 bits. accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-2: pic16f873a/874a program memory map and stack pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 page 1 page 2 page 3 07ffh 0800h 0fffh 1000h 17ffh 1800h pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw 1fffh stack level 2 program memory page 0 page 1 07ffh 0800h 0fffh 1000h
pic16f87xa ds39582b-page 16 ? 2003 microchip technology inc. 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 (status<6>) and rp0 (status<5>) are the bank select bits. each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some frequently used special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indirectly, through the file select register (fsr). rp1:rp0 bank 00 0 01 1 10 2 11 3 note: the eeprom data memory description can be found in section 3.0 ?data eeprom and flash program memory? of this data sheet.
? 2003 microchip technology inc. ds39582b-page 17 pic16f87xa figure 2-3: pic16f876a/877a register file map indirect addr. (*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspadd sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as ? 0 ?. * not a physical register. note 1: these registers are not implemented on the pic16f876a. 2: these registers are reserved; maintain these registers clear. file address indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 120h 1a0h 17fh 1ffh bank 2 bank 3 indirect addr. (*) portd (1) porte (1) trisd (1) adresl trise (1) tmr0 option_reg pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adresh adcon0 txsta spbrg adcon1 general purpose register general purpose register general purpose register general purpose register 1efh 1f0h accesses 70h - 7fh efh f0h accesses 70h-7fh 16fh 170h accesses 70h-7fh general purpose register general purpose register trisb portb 96 bytes 80 bytes 80 bytes 80 bytes 16 bytes 16 bytes sspcon2 eedata eeadr eecon1 eecon2 eedath eeadrh reserved (2) reserved (2) file address file address file address cmcon cvrcon
pic16f87xa ds39582b-page 18 ? 2003 microchip technology inc. figure 2-4: pic16f873a/874a register file map indirect addr. (*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspadd sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 indirect addr. (*) indirect addr. (*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 17fh 1ffh bank 2 bank 3 indirect addr. (*) portd (1) porte (1) trisd (1) adresl trise (1) tmr0 option_reg pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adresh adcon0 txsta spbrg adcon1 general purpose register general purpose register 1efh 1f0h accesses a0h - ffh 16fh 170h accesses 20h-7fh trisb portb 96 bytes 96 bytes sspcon2 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h eedata eeadr eecon1 eecon2 eedath eeadrh reserved (2) reserved (2) unimplemented data memory locations, read as ? 0 ?. * not a physical register. note 1: these registers are not implemented on the pic16f873a. 2: these registers are reserved; maintain these registers clear. 120h 1a0h file address file address file address file address cmcon cvrcon
? 2003 microchip technology inc. ds39582b-page 19 pic16f87xa 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral features section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: bank 0 00h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 31, 150 01h tmr0 timer0 module register xxxx xxxx 55, 150 02h (3) pcl program counter (pc) least significant byte 0000 0000 30, 150 03h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 22, 150 04h (3) fsr indirect data memory address pointer xxxx xxxx 31, 150 05h porta ? ? porta data latch when written: porta pins when read --0x 0000 43, 150 06h portb portb data latch when written: portb pins when read xxxx xxxx 45, 150 07h portc portc data latch when written: portc pins when read xxxx xxxx 47, 150 08h (4) portd portd data latch when written: portd pins when read xxxx xxxx 48, 150 09h (4) porte ? ? ? ? ? re2 re1 re0 ---- -xxx 49, 150 0ah (1,3) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 30, 150 0bh (3) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 24, 150 0ch pir1 pspif (3) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 26, 150 0dh pir2 ?cmif ?eeifbclif ? ?ccp2if -0-0 0--0 28, 150 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx 60, 150 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx 60, 150 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 57, 150 11h tmr2 timer2 module register 0000 0000 62, 150 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 61, 150 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx 79, 150 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 82, 82, 150 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx 63, 150 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx 63, 150 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 64, 150 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 112, 150 19h txreg usart transmit data register 0000 0000 118, 150 1ah rcreg usart receive data register 0000 0000 118, 150 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx 63, 150 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx 63, 150 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 64, 150 1eh adresh a/d result register high byte xxxx xxxx 133, 150 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 127, 150 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: bits pspie and pspif are reserved on pic16f873a/876a devices; always maintain these bits clear. 3: these registers can be addressed from any bank. 4: portd, porte, trisd and trise are not implemented on pic16f873a/876a devices, read as ? 0 ?. 5: bit 4 of eeadrh implemented only on the pic16f876a /877a devices.
pic16f87xa ds39582b-page 20 ? 2003 microchip technology inc. bank 1 80h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 31, 150 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 23, 150 82h (3) pcl program counter (pc) least significant byte 0000 0000 30, 150 83h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 22, 150 84h (3) fsr indirect data memory address pointer xxxx xxxx 31, 150 85h trisa ? ? porta data direction register --11 1111 43, 150 86h trisb portb data direction register 1111 1111 45, 150 87h trisc portc data direction register 1111 1111 47, 150 88h (4) trisd portd data direction register 1111 1111 48, 151 89h (4) trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 50, 151 8ah (1,3) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 30, 150 8bh (3) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 24, 150 8ch pie1 pspie (2) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 25, 151 8dh pie2 ?cmie ? eeie bclie ? ? ccp2ie -0-0 0--0 27, 151 8eh pcon ? ? ? ? ? ?por bor ---- --qq 29, 151 8fh ? unimplemented ? ? 90h ? unimplemented ? ? 91h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 83, 151 92h pr2 timer2 period register 1111 1111 62, 151 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 79, 151 94h sspstat smp cke d/a psr/w ua bf 0000 0000 79, 151 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 111, 151 99h spbrg baud rate generator register 0000 0000 113, 151 9ah ? unimplemented ? ? 9bh ? unimplemented ? ? 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 135, 151 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 141, 151 9eh adresl a/d result register low byte xxxx xxxx 133, 151 9fh adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 128, 151 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: bits pspie and pspif are reserved on pic16f873a/876a devices; always maintain these bits clear. 3: these registers can be addressed from any bank. 4: portd, porte, trisd and trise are not implemented on pic16f873a/876a devices, read as ? 0 ?. 5: bit 4 of eeadrh implemented only on the pic16f876a /877a devices.
? 2003 microchip technology inc. ds39582b-page 21 pic16f87xa bank 2 100h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 31, 150 101h tmr0 timer0 module register xxxx xxxx 55, 150 102h (3) pcl program counter?s (pc) least significant byte 0000 0000 30, 150 103h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 22, 150 104h (3) fsr indirect data memory address pointer xxxx xxxx 31, 150 105h ? unimplemented ? ? 106h portb portb data latch when written: portb pins when read xxxx xxxx 45, 150 107h ? unimplemented ? ? 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah (1,3) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 30, 150 10bh (3) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 24, 150 10ch eedata eeprom data register low byte xxxx xxxx 39, 151 10dh eeadr eeprom address register low byte xxxx xxxx 39, 151 10eh eedath ? ? eeprom data register high byte --xx xxxx 39, 151 10fh eeadrh ? ? ? ? (5) eeprom address register high byte ---- xxxx 39, 151 bank 3 180h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 31, 150 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 23, 150 182h (3) pcl program counter (pc) least significant byte 0000 0000 30, 150 183h (3) status irp rp1 rp0 to pd zdcc 0001 1xxx 22, 150 184h (3) fsr indirect data memory address pointer xxxx xxxx 31, 150 185h ? unimplemented ? ? 186h trisb portb data direction register 1111 1111 45, 150 187h ? unimplemented ? ? 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah (1,3) pclath ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 30, 150 18bh (3) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 24, 150 18ch eecon1 eepgd ? ? ? wrerr wren wr rd x--- x000 34, 151 18dh eecon2 eeprom control register 2 (not a physical register) ---- ---- 39, 151 18eh ? reserved; maintain clear 0000 0000 ? 18fh ? reserved; maintain clear 0000 0000 ? table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>, whose contents are transferred to the upper byte of the program counter. 2: bits pspie and pspif are reserved on pic16f873a/876a devices; always maintain these bits clear. 3: these registers can be addressed from any bank. 4: portd, porte, trisd and trise are not implemented on pic16f873a/876a devices, read as ? 0 ?. 5: bit 4 of eeadrh implemented only on the pic16f876a /877a devices.
pic16f87xa ds39582b-page 22 ? 2003 microchip technology inc. 2.2.2.1 status register the status register contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status reg- ister is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is dis- abled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable, therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status , will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf , swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions not affecting any status bits, see section 15.0 ?instruction set summary? . register 2-1: status register (address 03h, 83h, 103h, 183h) note: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h-1ffh) 0 = bank 0, 1 (00h-ffh) bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h-1ffh) 10 = bank 2 (100h-17fh) 01 = bank 1 (80h-ffh) 00 = bank 0 (00h-7fh) each bank is 128 bytes. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow , the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high, or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 23 pic16f87xa 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. register 2-2: option_reg register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: when using low-voltage icsp programming (lvp) and the pull-ups on portb are enabled, bit 3 in the trisb register must be cleared to disable the pull-up on rb3 and ensure the proper operation of the device 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16f87xa ds39582b-page 24 ? 2003 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peietmr0ieinte rbietmr0ifintf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state; a mismatch condition will continue to set the bit. reading portb will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 25 pic16f87xa 2.2.2.4 pie1 register the pie1 register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie: parallel slave port read/write interrupt enable bit (1) 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt note 1: pspie is reserved on pic16f873a/876a devices; always maintain this bit clear. bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 26 ? 2003 microchip technology inc. 2.2.2.5 pir1 register the pir1 register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1 register (address 0ch) note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif: parallel slave port read/write interrupt flag bit (1) 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred note 1: pspif is reserved on pic16f873a/876a devices; always maintain this bit clear. bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty 0 = the usart transmit buffer is full bit 3 sspif : synchronous serial port (ssp) interrupt flag bit 1 = the ssp interrupt condition has occurred and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi ? a transmission/reception has taken place. i 2 c slave ? a transmission/reception has taken place. i 2 c master - a transmission/reception has taken place. - the initiated start condition was completed by the ssp module. - the initiated stop condition was completed by the ssp module. - the initiated restart condition was completed by the ssp module. - the initiated acknowledge condition was completed by the ssp module. - a start condition occurred while the ssp module was idle (multi-master system). - a stop condition occurred while the ssp module was idle (multi-master system). 0 = no ssp interrupt condition has occurred bit 2 ccp1if : ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 27 pic16f87xa 2.2.2.6 pie2 register the pie2 register contains the individual enable bits for the ccp2 peripheral interrupt, the ssp bus collision interrupt, eeprom write operation interrupt and the comparator interrupt. register 2-6: pie2 register (address 8dh) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 ?cmie ? eeie bclie ? ? ccp2ie bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmie : comparator interrupt enable bit 1 = enables the comparator interrupt 0 = disable the comparator interrupt bit 5 unimplemented: read as ? 0 ? bit 4 eeie : eeprom write operation interrupt enable bit 1 = enable eeprom write interrupt 0 = disable eeprom write interrupt bit 3 bclie : bus collision interrupt enable bit 1 = enable bus collision interrupt 0 = disable bus collision interrupt bit 2-1 unimplemented: read as ? 0 ? bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 28 ? 2003 microchip technology inc. 2.2.2.7 pir2 register the pir2 register contains the flag bits for the ccp2 interrupt, the ssp bus collision interrupt, eeprom write operation interrupt and the comparator interrupt. register 2-7: pir2 register (address 0dh) note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 ?cmif ? eeif bclif ? ? ccp2if bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmif : comparator interrupt flag bit 1 = the comparator input has changed (must be cleared in software) 0 = the comparator input has not changed bit 5 unimplemented: read as ? 0 ? bit 4 eeif : eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3 bclif : bus collision interrupt flag bit 1 = a bus collision has occurred in the ssp when configured for i 2 c master mode 0 = no bus collision has occurred bit 2-1 unimplemented: read as ? 0 ? bit 0 ccp2if : ccp2 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 29 pic16f87xa 2.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watchdog reset (wdt) and an external mclr reset. register 2-8: pcon register (address 8eh) note: bor is unknown on power-on reset. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a ?don?t care? and is not predictable if the brown-out circuit is dis- abled (by clearing the boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 ? ? ? ? ? ?por bor bit 7 bit 0 bit 7-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 30 ? 2003 microchip technology inc. 2.3 pcl and pclath the program counter (pc) is 13 bits wide. the low byte comes from the pcl register which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 2-5 shows the two situations for the loading of the pc. the upper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in the figure shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 2-5: loading of pc in different situations 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to the application note, an556, ?implementing a table read? (ds00556). 2.3.2 stack the pic16f87xa family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an interrupt causes a branch. the stack is pop?ed in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging all pic16f87xa devices are capable of addressing a continuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruc- tion, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is popped off the stack. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). example 2-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 2-1: call of a subroutine in page 1 from page 0 pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call , return , retlw and retfie instructions or the vectoring to an interrupt address. note: the contents of the pclath register are unchanged after a return or retfie instruction is executed. the user must rewrite the contents of the pclath regis- ter for any subsequent subroutine calls or goto instructions. org 0x500 bcf pclath,4 bsf pclath,3 ;select page 1 ;(800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine ;page 1 (800h-fffh) : return ;return to ;call subroutine ;in page 0 ;(000h-7ffh)
? 2003 microchip technology inc. ds39582b-page 31 pic16f87xa 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself, indirectly (fsr = 0 ) will read 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>) as shown in figure 2-6. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: indirect addressing figure 2-6: direct/indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue note 1: for register file map detail, see figure 2-3. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
pic16f87xa ds39582b-page 32 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 33 pic16f87xa 3.0 data eeprom and flash program memory the data eeprom and flash program memory is read- able and writable during normal operation (over the full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers. there are six sfrs used to read and write this memory: eecon1 eecon2 eedata eedath eeadr eeadrh when interfacing to the data memory block, eedata holds the 8-bit data for read/write and eeadr holds the address of the eeprom location being accessed. these devices have 128 or 256 bytes of data eeprom (depending on the device), with an address range from 00h to ffh. on devices with 128 bytes, addresses from 80h to ffh are unimplemented and will wraparound to the beginning of data eeprom memory. when writing to unimplemented locations, the on-chip charge pump will be turned off. when interfacing the program memory block, the eedata and eedath registers form a two-byte word that holds the 14-bit data for read/write and the eeadr and eeadrh registers form a two-byte word that holds the 13-bit address of the program memory location being accessed. these devices have 4 or 8k words of program flash, with an address range from 0000h to 0fffh for the pic16f873a/874a and 0000h to 1fffh for the pic16f876a/877a. addresses above the range of the respective device will wraparound to the beginning of program memory. the eeprom data memory allows single-byte read and write. the flash program memory allows single-word reads and four-word block writes. program memory write operations automatica lly perform an erase-before- write on blocks of four words. a byte write in data eeprom memory automatically erases the location and writes the new data (erase-before-write). the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device for byte or word operations. when the device is code-protected, the cpu may continue to read and write the data eeprom memory. depending on the settings of the write-protect bits, the device may or may not be able to write certain blocks of the program memory; however, reads of the program memory are allowed. when code-protected, the device programmer can no longer access data or program memory; this does not inhibit internal reads or writes. 3.1 eeadr and eeadrh the eeadrh:eeadr register pair can address up to a maximum of 256 bytes of data eeprom or up to a maximum of 8k words of program eeprom. when selecting a data address value, only the lsbyte of the address is written to the eeadr register. when select- ing a program address value, the msbyte of the address is written to the eeadrh register and the lsbyte is written to the eeadr register. if the device contains less memory than the full address reach of the address register pair, the most significant bits of the registers are not implemented. for example, if the device has 128 bytes of data eeprom, the most significant bit of eeadr is not implemented on access to data eeprom. 3.2 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. control bit, eepgd, determines if the access will be a program or data memory access. when clear, as it is when reset, any subsequent operations will operate on the data memory. when set, any subsequent operations will operate on the program memory. control bits, rd and wr, initiate read and write or erase, respectively. these bits cannot be cleared, only set, in software. they are cleared in hardware at com- pletion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write or erase operation. on power-up, the wren bit is clear. the wrerr bit is set when a write (or erase) operation is interrupted by a mclr or a wdt time-out reset dur- ing normal operation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the data and address will be unchanged in the eedata and eeadr registers. interrupt flag bit, eeif in the pir2 register, is set when the write is complete. it must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the eeprom write sequence. note: the self-programming mechanism for flash program memory has been changed. on previous pic16f87x devices, flash pro- gramming was done in single-word erase/ write cycles. the newer pic18f87xa devices use a four-word erase/write cycle. see section 3.6 ?writing to flash program memory? for more information.
pic16f87xa ds39582b-page 34 ? 2003 microchip technology inc. register 3-1: eecon1 register (address 18ch) r/w-x u-0 u-0 u-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd ? ? ? wrerr wren wr rd bit 7 bit 0 bit 7 eepgd : program/data eeprom select bit 1 = accesses program memory 0 = accesses data memory reads ? 0 ? after a por; this bit cannot be changed while a write operation is in progress. bit 6-4 unimplemented: read as ? 0 ? bit 3 wrerr: eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr or any wdt reset during normal operation) 0 = the write operation completed bit 2 wren: eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom bit 1 wr: write control bit 1 = initiates a write cycle. the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software. 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read; rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 35 pic16f87xa 3.3 reading data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd con- trol bit (eecon1<7>) and then set control bit rd (eecon1<0>). the data is available in the very next cycle in the eedata register; therefore, it can be read in the next instruction (see example 3-1). eedata will hold this value until another read or until it is written to by the user (during a write operation). the steps to reading the eeprom data memory are: 1. write the address to eeadr. make sure that the address is not larger than the memory size of the device. 2. clear the eepgd bit to point to eeprom data memory. 3. set the rd bit to start the read operation. 4. read the data from the eedata register. example 3-1: data eeprom read 3.4 writing to data eeprom memory to write an eeprom data location, the user must first write the address to the eeadr register and the data to the eedata register. then the user must follow a specific write sequence to initiate the write for each byte. the write will not initiate if the write sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment (see example 3-2). additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating eeprom. the wren bit is not cleared by hardware after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. eeif must be cleared by software. the steps to write to eeprom data memory are: 1. if step 10 is not implemented, check the wr bit to see if a write is in progress. 2. write the address to eeadr. make sure that the address is not larger than the memory size of the device. 3. write the 8-bit data value to be programmed in the eedata register. 4. clear the eepgd bit to point to eeprom data memory. 5. set the wren bit to enable program operations. 6. disable interrupts (if enabled). 7. execute the special five instruction sequence: write 55h to eecon2 in two steps (first to w, then to eecon2) write aah to eecon2 in two steps (first to w, then to eecon2) set the wr bit 8. enable interrupts (if using interrupts). 9. clear the wren bit to disable program operations. 10. at the completion of the write cycle, the wr bit is cleared and the eeif interrupt flag bit is set. (eeif must be cleared by firmware.) if step 1 is not implemented, then firmware should check for eeif to be set, or wr to clear, to indicate the end of the program cycle. example 3-2: data eeprom write bsf status,rp1 ; bcf status,rp0 ; bank 2 movf data_ee_addr,w ; data memory movwf eeadr ; address to read bsf status,rp0 ; bank 3 bcf eecon1,eepgd ; point to data ; memory bsf eecon1,rd ; ee read bcf status,rp0 ; bank 2 movf eedata,w ; w = eedata bsf status,rp1 ; bsf status,rp0 btfsc eecon1,wr ;wait for write goto $-1 ;to complete bcf status, rp0 ;bank 2 movf data_ee_addr,w ;data memory movwf eeadr ;address to write movf data_ee_data,w ;data memory value movwf eedata ;to write bsf status,rp0 ;bank 3 bcf eecon1,eepgd ;point to data ;memory bsf eecon1,wren ;enable writes bcf intcon,gie ;disable ints. movlw 55h ; movwf eecon2 ;write 55h movlw aah ; movwf eecon2 ;write aah bsf eecon1,wr ;set wr bit to ;begin write bsf intcon,gie ;enable ints. bcf eecon1,wren ;disable writes required sequence
pic16f87xa ds39582b-page 36 ? 2003 microchip technology inc. 3.5 reading flash program memory to read a program memory location, the user must write two bytes of the address to the eeadr and eeadrh registers, set the eepgd control bit (eecon1<7>) and then set control bit rd (eecon1<0>). once the read control bit is set, the program memory flash controller will use the next two instruction cycles to read the data. this causes these two instructions immediately follow- ing the ? bsf eecon1,rd ? instruction to be ignored. the data is available in the very next cycle in the eedata and eedath registers; therefore, it can be read as two bytes in the following instructions. eedata and eedath registers will hold this value until another read or until it is written to by the user (during a write operation). example 3-3: flash program read bsf status, rp1 ; bcf status, rp0 ; bank 2 movlw ms_prog_ee_addr ; movwf eeadrh ; ms byte of program address to read movlw ls_prog_ee_addr ; movwf eeadr ; ls byte of program address to read bsf status, rp0 ; bank 3 bsf eecon1, eepgd ; point to program memory bsf eecon1, rd ; ee read ; nop nop ; any instructions here are ignored as program ; memory is read in second cycle after bsf eecon1,rd ; bcf status, rp0 ; bank 2 movf eedata, w ; w = ls byte of program eedata movwf datal ; movf eedath, w ; w = ms byte of program eedata movwf datah ; required sequence
? 2003 microchip technology inc. ds39582b-page 37 pic16f87xa 3.6 writing to flash program memory flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits wrt1:wrt0 of the device configuration word (register 14-1). flash program memory must be written in four-word blocks. a block consists of four words with sequential addresses, with a lower boundary defined by an address, where eeadr<1:0> = 00 . at the same time, all block writes to program memory are done as erase and write opera- tions. the write operation is edge-aligned and cannot occur across boundaries. to write program data, it must first be loaded into the buffer registers (see figure 3-1). this is accomplished by first writing the destination address to eeadr and eeadrh and then writing the data to eedata and eedath. after the address and data have been set up, then the following sequence of events must be executed: 1. set the eepgd control bit (eecon1<7>). 2. write 55h, then aah, to eecon2 (flash programming sequence). 3. set the wr control bit (eecon1<1>). all four buffer register locations must be written to with correct data. if only one, two or three words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed. this takes the data from the pro- gram location(s) not being written and loads it into the eedata and eedath registers. then the sequence of events to transfer data to the buffer registers must be executed. to transfer data from the buff er registers to the program memory, the eeadr and eeadrh must point to the last location in the four-word block (eeadr<1:0> = 11 ). then the following sequence of events must be executed: 1. set the eepgd control bit (eecon1<7>). 2. write 55h, then aah, to eecon2 (flash programming sequence). 3. set control bit wr (eecon1<1>) to begin the write operation. the user must follow the same specific sequence to ini- tiate the write for each word in the program block, writ- ing each program word in sequence ( 00,01,10,11 ). when the write is performed on the last word (eeadr<1:0> = 11 ), the block of four words are automatically erased and the contents of the buffer registers are written into the program memory. after the ? bsf eecon1,wr ? instruction, the processor requires two cycles to set up the erase/write operation. the user must place two nop instructions after the wr bit is set. since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. the processor will halt internal operations for the typical 4 ms, only during the cycle in which the erase takes place (i.e., the last word of the four-word block). this is not sleep mode as the clocks and peripherals will continue to run. after the write cycle, the processor will resume operation with the third instruction after the eecon1 write instruction. if the sequence is performed to any other location, the action is ignored. figure 3-1: block writes to flash program memory 14 14 14 14 program memory buffer register eeadr<1:0> = 00 buffer register eeadr<1:0> = 01 buffer register eeadr<1:0> = 10 buffer register eeadr<1:0> = 11 eedata eedath 75 07 0 6 8 first word of block to be written four words of to flash automatically after this word is written are transferred flash are erased, then all buffers
pic16f87xa ds39582b-page 38 ? 2003 microchip technology inc. an example of the complete four-word write sequence is shown in example 3-4. the initial address is loaded into the eeadrh:eeadr register pair; the four words of data are loaded using indirect addressing. example 3-4: writing to flash program memory ; this write routine assumes the following: ; ; 1. a valid starting address (the least significant bits = ?00?)is loaded in addrh:addrl ; 2. the 8 bytes of data are loaded, starting at the address in dataddr ; 3. addrh, addrl and dataddr are all located in shared data memory 0x70 - 0x7f ; bsf status,rp1 ; bcf status,rp0 ; bank 2 movf addrh,w ; load initial address movwf eeadrh ; movf addrl,w ; movwf eeadr ; movf dataaddr,w ; load initial data address movwf fsr ; loop movf indf,w ; load first data byte into lower movwf eedata ; incf fsr,f ; next byte movf indf,w ; load second data byte into upper movwf eedath ; incf fsr,f ; bsf status,rp0 ; bank 3 bsf eecon1,eepgd ; point to program memory bsf eecon1,wren ; enable writes bcf intcon,gie ; disable interrupts (if using) movlw 55h ; start of required write sequence: movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit to begin write nop ; any instructions here are ignored as processor ; halts to begin write sequence nop ; processor will stop here and wait for write complete ; after write processor continues with 3rd instruction bcf eecon1,wren ; disable writes bsf intcon,gie ; enable interrupts (if using) bcf status,rp0 ; bank 2 incf eeadr,f ; increment address movf eeadr,w ; check if lower two bits of address are ?00? andlw 0x03 ; indicates when four words have been programmed xorlw 0x03 ; btfsc status,z ; exit if more than four words, goto loop ; continue if less than four words required sequence
? 2003 microchip technology inc. ds39582b-page 39 pic16f87xa 3.7 protection against spurious write there are conditions when the device should not write to the data eeprom or flash program memory. to protect against spurious writes, various mechanisms have been built-in. on power-up, wren is cleared. also, the power-up timer (72 ms duration) prevents an eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 3.8 operation during code-protect when the data eeprom is code-protected, the micro- controller can read and write to the eeprom normally. however, all external access to the eeprom is disabled. external write access to the program memory is also disabled. when program memory is code-protected, the microcon- troller can read and write to program memory normally, as well as execute instructions. writes by the device may be selectively inhibited to regions of the memory depend- ing on the setting of bits wr1:wr0 of the configuration word (see section 14.1 ?configuration bits? for addi- tional information). external access to the memory is also disabled. table 3-1: registers/bits associated with data eeprom and flash program memories address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 10ch eedata eeprom/flash data register low byte xxxx xxxx uuuu uuuu 10dh eeadr eeprom/flash address register low byte xxxx xxxx uuuu uuuu 10eh eedath ? ? eeprom/flash data register high byte xxxx xxxx ---0 q000 10fh eeadrh ? ? ? eeprom/flash address register high byte xxxx xxxx ---- ---- 18ch eecon1 eepgd ? ? ? wrerr wren wr rd x--- x000 ---0 q000 18dh eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- 0dh pir2 ? cmif ?eeif bclif ? ? ccp2if -0-0 0--0 -0-0 0--0 8dh pie2 ? cmie ?eeie bclie ? ? ccp2ie -0-0 0--0 -0-0 0--0 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends upon condition. shaded cells are not used by data eeprom or flash program memory.
pic16f87xa ds39582b-page 40 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 41 pic16f87xa 4.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro? mid-range reference manual (ds33023). 4.1 porta and the trisa register porta is a 6-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open-drain output. all other porta pins have ttl input levels and full cmos output drivers. other porta pins are multiplexed with analog inputs and the analog v ref input for both the a/d converters and the comparators. the operation of each pin is selected by clearing/setting the appropriate control bits in the adcon1 and/or cmcon registers. the trisa register controls the direction of the port pins even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 4-1: initializing porta figure 4-1: block diagram of ra3:ra0 pins note: on a power-on reset, these pins are con- figured as analog inputs and read as ? 0 ?. the comparators are in the off (digital) state. bcf status, rp0 ; bcf status, rp1 ; bank0 clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6>are always ; read as '0'. data bus q d q ck q d q ck qd en p n wr porta wr trisa data latch tris latch rd rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter or comparator trisa
pic16f87xa ds39582b-page 42 ? 2003 microchip technology inc. figure 4-2: block diagram of ra4/t0cki pin figure 4-3: block diag ram of ra5 pin data bus wr porta wr trisa rd porta data latch tris latch rd trisa schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en c1out note 1: i/o pin has protection diodes to v ss only. cmcon<2:0> = x01 or 011 1 0 data bus wr porta wr trisa rd porta data latch tris latch rd trisa ttl input buffer i/o pin (1) a/d converter or ss input q d q ck q d q ck en qd en c2out cmcon<2:0> = 011 or 101 1 0 p n v ss v dd note 1: i/o pin has protection diodes to v dd and v ss . analog i ip mode
? 2003 microchip technology inc. ds39582b-page 43 pic16f87xa table 4-1: porta functions table 4-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2/v ref -/cv ref bit 2 ttl input/output or analog input or v ref - or cv ref . ra3/an3/v ref + bit 3 ttl input/output or analog input or v ref +. ra4/t0cki/c1out bit 4 st input/output or external clock input for timer0 or comparator output. output is open-drain type. ra5/an4/ss /c2out bit 5 ttl input/output or analog input or slave select input for synchronous serial port or comparator output. legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 9fh adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 00-- 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note: when using the ssp module in spi slave mode and ss enabled, the a/d converter must be set to one of the following modes, where pcfg3:pcfg0 = 0100, 0101, 011x, 1101, 1110, 1111 .
pic16f87xa ds39582b-page 44 ? 2003 microchip technology inc. 4.2 portb and the trisb register portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). three pins of portb are multiplexed with the in-circuit debugger and low-voltage programming function: rb3/pgm, rb6/pgc and rb7/pgd. the alternate functions of these pins are described in section 14.0 ?special features of the cpu? . each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. figure 4-4: block diagram of rb3:rb0 pins four of the portb pins, rb7:rb4, have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are or?ed together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. this interrupt-on-mismatch feature, together with soft- ware configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the application note, an552, ?implementing wake-up on key stroke? (ds00552). rb0/int is an external interrupt input pin and is configured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 14.11.1 ?int interrupt? . figure 4-5: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). rb3/pgm data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer st buffer rb7:rb6 q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). in serial programming mode
? 2003 microchip technology inc. ds39582b-page 45 pic16f87xa table 4-3: portb functions table 4-4: summary of registers associated with portb name bit# buffer function rb0/int bit 0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit 1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit 2 ttl input/output pin. internal software programmable weak pull-up. rb3/pgm (3) bit 3 ttl input/output pin or programming pin in lvp mode. internal software programmable weak pull-up. rb4 bit 4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit 5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6/pgc bit 6 ttl/st (2) input/output pin (with interrupt-on-change) or in-circuit debugger pin. internal software programmable weak pull-up. serial programming clock. rb7/pgd bit 7 ttl/st (2) input/output pin (with interrupt-on-change) or in-circuit debugger pin. internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode or in-circuit debugger. 3: low-voltage icsp programming (lvp) is enabled by default which disables the rb3 i/o function. lvp must be disabled to enable rb3 as an i/o pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16f87xa ds39582b-page 46 ? 2003 microchip technology inc. 4.3 portc and the trisc register portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 4-5). portc pins have schmitt trigger input buffers. when the i 2 c module is enabled, the portc<4:3> pins can be configured with normal i 2 c levels, or with smbus levels, by using the cke bit (sspstat<6>). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf , bcf , xorwf ) with trisc as the destination, should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. figure 4-6: portc block diagram (peripheral output override) rc<2:0>, rc<7:5> figure 4-7: portc block diagram (peripheral output override) rc<4:3> port/peripheral select (2) data bus wr port wr tris data latch tris latch schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. rd tris port/peripheral select (2) data bus wr port wr tris data latch tris latch schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd port peripheral oe (3) ssp input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. 0 1 cke sspstat<6> schmitt trigger with smbus levels rd tris
? 2003 microchip technology inc. ds39582b-page 47 pic16f87xa table 4-5: portc functions table 4-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit 0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit 1 st input/output port pin or timer1 oscillator input or capture2 input/ compare2 output/pwm2 output. rc2/ccp1 bit 2 st input/output port pin or capture1 input/compare1 output/ pwm1 output. rc3/sck/scl bit 3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit 4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit 6 st input/output port pin or usart asynchronous transmit or synchronous clock. rc7/rx/dt bit 7 st input/output port pin or usart asynchronous receive or synchronous data. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
pic16f87xa ds39582b-page 48 ? 2003 microchip technology inc. 4.4 portd and trisd registers portd is an 8-bit port with schmitt trigger input buffers. each pin is individually configurable as an input or output. portd can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit, pspmode (trise<4>). in this mode, the input buffers are ttl. figure 4-8: portd block diagram (in i/o port mode) table 4-7: portd functions table 4-8: summary of registers associated with portd note: portd and trisd are not implemented on the 28-pin devices. data bus wr port wr tris rd port data latch tris latch rd schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en tris name bit# buffer type function rd0/psp0 bit 0 st/ttl (1) input/output port pin or parallel slave port bit 0. rd1/psp1 bit 1 st/ttl (1) input/output port pin or parallel slave port bit 1. rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit 2. rd3/psp3 bit 3 st/ttl (1) input/output port pin or parallel slave port bit 3. rd4/psp4 bit 4 st/ttl (1) input/output port pin or parallel slave port bit 4. rd5/psp5 bit 5 st/ttl (1) input/output port pin or parallel slave port bit 5. rd6/psp6 bit 6 st/ttl (1) input/output port pin or parallel slave port bit 6. rd7/psp7 bit 7 st/ttl (1) input/output port pin or parallel slave port bit 7. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by portd.
? 2003 microchip technology inc. ds39582b-page 49 pic16f87xa 4.5 porte and trise register porte has three pins (re0/rd /an5, re1/wr /an6 and re2/cs /an7) which are individually configurable as inputs or outputs. these pins have schmitt trigger input buffers. the porte pins become the i/o control inputs for the microprocessor port when bit pspmode (trise<4>) is set. in this mode, the user must make certain that the trise<2:0> bits are set and that the pins are configured as digital inputs. also, ensure that adcon1 is config- ured for digital i/o. in this mode, the input buffers are ttl. register 4-1 shows the trise register which also controls the parallel slave port operation. porte pins are multiplexed with analog inputs. when selected for analog input, these pins will read as ? 0 ?s. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. figure 4-9: porte block diagram (in i/o port mode) table 4-9: porte functions note: porte and trise are not implemented on the 28-pin devices. note: on a power-on reset, these pins are configured as analog inputs and read as ? 0 ?. data bus wr port wr tris rd port data latch tris latch rd schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . tris name bit# buffer type function re0/rd /an5 bit 0 st/ttl (1) i/o port pin or read control input in parallel slave port mode or analog input: rd 1 =idle 0 = read operation. contents of portd register are output to portd i/o pins (if chip selected). re1/wr /an6 bit 1 st/ttl (1) i/o port pin or write control input in parallel slave port mode or analog input: wr 1 =idle 0 = write operation. value of portd i/o pins is latched into portd register (if chip selected). re2/cs /an7 bit 2 st/ttl (1) i/o port pin or chip select control input in parallel slave port mode or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode.
pic16f87xa ds39582b-page 50 ? 2003 microchip technology inc. table 4-10: summary of registers associated with porte register 4-1: trise register (address 89h) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 9fh adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 00-- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by porte. r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? bit 2bit 1bit 0 bit 7 bit 0 parallel slave port status/control bits: bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = portd functions in parallel slave port mode 0 = portd functions in general purpose i/o mode bit 3 unimplemented : read as ? 0 ? porte data direction bits: bit 2 bit 2 : direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1 bit 1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0 bit 0 : direction control bit for pin re0/rd /an5 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 51 pic16f87xa 4.6 parallel slave port the parallel slave port (psp) is not implemented on the pic16f873a or pic16f876a. portd operates as an 8-bit wide parallel slave port, or microprocessor port, when control bit pspmode (trise<4>) is set. in slave mode, it is asynchronously readable and writable by the external world through rd control input pin, re0/rd /an5, and wr control input pin, re1/wr /an6. the psp can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd /an5 to be the rd input, re1/wr /an6 to be the wr input and re2/cs /an7 to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). the a/d port configuration bits, pcfg3:pcfg0 (adcon1<3:0>), must be set to configure pins re2:re0 as digital i/o. there are actually two 8-bit latches: one for data output and one for data input. the user writes 8-bit data to the portd data latch and reads data from the port pin latch (note that they have the same address). in this mode, the trisd register is ignored since the external device is controlling the direction of data flow. a write to the psp occurs when both the cs and wr lines are first detected low. when either the cs or wr lines become high (level triggered), the input buffer full (ibf) status flag bit (trise<7>) is set on the q4 clock cycle, following the next q2 cycle, to signal the write is complete (figure 4-11). the interrupt flag bit, pspif (pir1<7>), is also set on the same q4 clock cycle. ibf can only be cleared by reading the portd input latch. the input buffer overflow (ibov) status flag bit (trise<5>) is set if a second write to the psp is attempted when the previous byte has not been read out of the buffer. a read from the psp occurs when both the cs and rd lines are first detected low. the output buffer full (obf) status flag bit (trise<6>) is cleared immediately (figure 4-12), indicating that the portd latch is waiting to be read by the external bus. when either the cs or rd pin becomes high (level triggered), the interrupt flag bit pspif is set on the q4 clock cycle, following the next q2 cycle, indicating that the read is complete. obf remains low until data is written to portd by the user firmware. when not in psp mode, the ibf and obf bits are held clear. however, if flag bit ibov was previously set, it must be cleared in firmware. an interrupt is generated and latched into flag bit pspif when a read or write operation is completed. pspif must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). figure 4-10: portd and porte block diagram (parallel slave port) data bus wr port rd port rdx pin q d ck en qd en one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr ttl ttl ttl ttl note 1: i/o pins have protection diodes to v dd and v ss .
pic16f87xa ds39582b-page 52 ? 2003 microchip technology inc. figure 4-11: parallel slave port write waveforms figure 4-12: parallel slave port read waveforms table 4-11: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd port data latch when written; port pins when read xxxx xxxx uuuu uuuu 09h porte ? ? ? ? ?re2re1re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 00-- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. note 1: bits pspie and pspif are reserved on the pic16f873a/876a; always maintain these bits clear.
? 2003 microchip technology inc. ds39582b-page 53 pic16f87xa 5.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock figure 5-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. additional information on the timer0 module is available in the picmicro ? mid-range mcu family reference manual (ds33023). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 register is written, the incre- ment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit, t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in detail in section 5.2 ?using timer0 with an external clock? . the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the prescaler is not readable or writable. section 5.3 ?prescaler? details the operation of the prescaler. 5.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h. this overflow sets bit tmr0if (intcon<2>). the interrupt can be masked by clearing bit tmr0ie (intcon<5>). bit tmr0if must be cleared in software by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut-off during sleep. figure 5-1: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clko (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m u x mux watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit tmr0if on overflow 8 psa t0cs prescaler
pic16f87xa ds39582b-page 54 ? 2003 microchip technology inc. 5.2 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 20 ns) and low for at least 2 t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 5.3 prescaler there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer and vice versa. this prescaler is not readable or writable (see figure 5-1). the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. register 5-1: option_reg register note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu bit 6 intedg bit 5 t0cs : tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: to avoid an unintended device reset, the instruction sequence shown in the picmicro ? mid-range mcu family reference manual (ds33023) must be exe- cuted when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 2003 microchip technology inc. ds39582b-page 55 pic16f87xa table 5-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by timer0.
pic16f87xa ds39582b-page 56 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 57 pic16f87xa 6.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l) which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit, tmr1ie (pie1<0>). timer1 can operate in one of two modes: as a timer as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit, tmr1on (t1con<0>). timer1 also has an internal ?reset input?. this reset can be generated by either of the two ccp modules ( section 8.0 ?capture/compare/pwm modules? ). register 6-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored and these pins read as ? 0 ?. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). register 6-1: t1con: timer1 co ntrol register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 t1sync : timer1 external clock input synchronization control bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 58 ? 2003 microchip technology inc. 6.1 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit, t1sync (t1con<2>), has no effect since the internal clock is always in sync. 6.2 timer1 counter operation timer1 may operate in either a synchronous, or an asynchronous mode, depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. figure 6-1: timer1 incrementing edge 6.3 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2 when bit t1oscen is set, or on pin rc0/t1oso/t1cki when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the prescaler stage is an asynchronous ripple counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present since the synchronization circuit is shut-off. the prescaler, however, will continue to increment. figure 6-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 q clock t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi/ccp2 (2) note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1
? 2003 microchip technology inc. ds39582b-page 59 pic16f87xa 6.4 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt-on-overflow which will wake-up the processor. however, special precautions in software are needed to read/write the timer. in asynchronous counter mode, timer1 cannot be used as a time base for capture or compare operations. 6.4.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. examples 12-2 and 12-3 in the picmicro ? mid-range mcu family reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 6.5 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit, t1oscen (t1con<3>). the oscil- lator is a low-power oscillator, rated up to 200 khz. it will continue to run during sleep. it is primarily intended for use with a 32 khz crystal. table 6-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 6-1: capacitor selection for the timer1 oscillator 6.6 resetting timer1 using a ccp trigger output if the ccp1 or ccp2 module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1. timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1 or ccp2, the write will take precedence. in this mode of operation, the ccprxh:ccprxl regis- ter pair effectively becomes the period register for timer1. osc type freq. c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. note: the special event triggers from the ccp1 and ccp2 modules will not set interrupt flag bit, tmr1if (pir1<0>).
pic16f87xa ds39582b-page 60 ? 2003 microchip technology inc. 6.7 resetting of timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 and ccp2 special event triggers. t1con register is reset to 00h on a power-on reset, or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 6.8 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. table 6-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: bits pspie and pspif are reserved on the 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39582b-page 61 pic16f87xa 7.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time base for the pwm mode of the ccp module(s). the tmr2 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit, tmr2if (pir1<1>)). timer2 can be shut-off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. register 7-1 shows the timer2 control register. additional information on timer modules is available in the picmicro ? mid-range mcu family reference manual (ds33023). figure 7-1: timer2 block diagram register 7-1: t2con: timer2 co ntrol register (address 12h) comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. t2outps3: t2outps0 t2ckps1: t2ckps0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 62 ? 2003 microchip technology inc. 7.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (por, mclr reset, wdt reset or bor) tmr2 is not cleared when t2con is written. 7.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the ssp module, which optionally uses it to generate the shift clock. table 7-1: registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module?s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39582b-page 63 pic16f87xa 8.0 capture/compare/pwm modules each capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: 16-bit capture register 16-bit compare register pwm master/slave duty cycle register both the ccp1 and ccp2 modules are identical in operation, with the exception being the operation of the special event trigger. table 8-1 and table 8-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 operates the same as ccp1 except where noted. ccp1 module: capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match and will reset timer1. ccp2 module: capture/compare/pwm register 2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. the special event trigger is generated by a compare match and will reset timer1 and start an a/d conversion (if the a/d module is enabled). additional information on ccp modules is available in the picmicro ? mid-range mcu family reference manual (ds33023) and in application note an594, ?using the ccp module(s)? (ds00594). table 8-1: ccp mode ? timer resources required table 8-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time base capture compare the compare should be configured for the special event trigger which clears tmr1 compare compare the compare(s) should be configured for the special event trigger which clears tmr1 pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt) pwm capture none pwm compare none
pic16f87xa ds39582b-page 64 ? 2003 microchip technology inc. register 8-1: ccp1con register/ccp2con register (address 17h/1dh) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ccpxx:ccpxy : pwm least significant bits capture mode : unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set, ccpx pin is unaffected); ccp1 resets tmr1; ccp2 resets tmr1 and starts an a/d conversion (if a/d module is enabled) 11xx = pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 65 pic16f87xa 8.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the type of event is configured by control bits, ccp1m3:ccp1m0 (ccpxcon<3:0>). when a cap- ture is made, the interrupt request flag bit, ccp1if (pir1<2>), is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new value. 8.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be configured as an input by setting the trisc<2> bit. figure 8-1: capture mode operation block diagram 8.1.2 timer1 mode selection timer1 must be running in timer mode, or synchro- nized counter mode, for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit, ccp1if, following any such change in operating mode. 8.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 8-1: changing between capture prescalers note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler 1, 4, 16 and edge detect pin clrf ccp1con ; turn ccp module off movlw new_capt_ps ; load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ; load ccp1con with this ; value
pic16f87xa ds39582b-page 66 ? 2003 microchip technology inc. 8.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits, ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 8-2: compare mode operation block diagram 8.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an output by clearing the trisc<2> bit. 8.2.2 timer1 mode selection timer1 must be running in timer mode, or synchro- nized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.2.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccpif bit is set, causing a ccp interrupt (if enabled). 8.2.4 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp2 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>) and set bit go/done (adcon0<2>). note: the special event trigger from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>).
? 2003 microchip technology inc. ds39582b-page 67 pic16f87xa 8.3 pwm mode (pwm) in pulse width modulation mode, the ccpx pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 8-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 8.3.3 ?setup for pwm operation? . figure 8-3: simplified pwm block diagram a pwm output (figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: pwm output 8.3.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 8.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle =(ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitch-free pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the following formula. equation 8-1: note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: the 8-bit timer is concatenated with 2-bit internal q clock, or 2 bits of the prescaler, to create 10-bit time base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 7.1 ?timer2 prescaler and postscaler? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits resolution =
pic16f87xa ds39582b-page 68 ? 2003 microchip technology inc. 8.3.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 8-3: example pwm frequencies and resolutions at 20 mhz table 8-4: registers associated with capture, compare and timer1 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xffh 0xffh 0xffh 0x3fh 0x1fh 0x17h maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ?ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not us ed by capture and timer1. note 1: the psp is not implemented on 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39582b-page 69 pic16f87xa table 8-5: registers associated with pwm and timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ?ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module?s register 0000 0000 0000 0000 92h pr2 timer2 module?s period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
pic16f87xa ds39582b-page 70 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 71 pic16f87xa 9.0 master synchronous serial port (mssp) module 9.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode 9.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon and sspcon2). the use of these registers and their individual configuration bits differ significantly, depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 9.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) ? rc5/sdo serial data in (sdi) ? rc4/sdi/sda serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) ? ra5/an4/ss /c2out figure 9-1 shows the block diagram of the mssp module when operating in spi mode. figure 9-1: mssp block diagram (spi mode) note: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the state of the ss pin can affect the state read back from the trisc<5> bit. the peripheral oe signal from the ssp mod- ule in portc controls the state that is read back from the trisc<5> bit (see section 4.3 ?portc and the trisc register? for information on portc). if read-modify-write instructions, such as bsf , are performed on the trisc register while the ss pin is high, this will cause the trisc<5> bit to be set, thus disabling the sdo output. read write internal data bus sspsr reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke rc5/sdo ( ) sspbuf reg rc4/sdi/sda ra5/an4/ rc3/sck/scl peripheral oe ss /c2out
pic16f87xa ds39582b-page 72 ? 2003 microchip technology inc. 9.3.1 registers the mssp module has four registers for spi mode operation. these are: mssp control register (sspcon) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) ? not directly accessible sspcon and sspstat are the control and status registers in spi mode operation. the sspcon regis- ter is readable and writable. the lower six bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. register 9-1: sspstat: mssp status register (spi mode) (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock select bit 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state note: polarity of clock state is set by the ckp bit (sspcon1<4>). bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write bit information used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 73 pic16f87xa register 9-2: sspcon1: mssp control register 1 (spi mode) (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word. (must be cleared in software.) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. (must be cleared in software.) 0 = no overflow note: in master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the sspbuf register. bit 5 sspen: synchronous serial port enable bit 1 = enables serial port and configures sck, sdo, sdi, and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 74 ? 2003 microchip technology inc. 9.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon<5:0> and sspstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the eight bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf (sspstat<0>), and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 9-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indicates the various status conditions. example 9-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received(transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 2003 microchip technology inc. ds39582b-page 75 pic16f87xa 9.3.3 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, re-initialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed. that is: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ss must have trisc<4> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 9.3.4 typical connection figure 9-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data ? slave sends dummy data master sends data ? slave sends data master sends dummy data ? slave sends data figure 9-2: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010xb serial clock
pic16f87xa ds39582b-page 76 ? 2003 microchip technology inc. 9.3.5 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 9-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon<4>). this then, would give waveforms for spi communication as shown in figure 9-3, figure 9-5 and figure 9-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 9-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 9-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2
? 2003 microchip technology inc. ds39582b-page 77 pic16f87xa 9.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 9.3.7 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 9-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2
pic16f87xa ds39582b-page 78 ? 2003 microchip technology inc. figure 9-5: spi mode waveform (slave mode with cke = 0 ) figure 9-6: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
? 2003 microchip technology inc. ds39582b-page 79 pic16f87xa 9.3.8 sleep operation in master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device from sleep. 9.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 9.3.10 bus mode compatibility table 9-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 9-1: spi bus modes there is also a smp bit which controls when the data is sampled. table 9-2: registers associated with spi operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa ? porta data direction register --11 1111 --11 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi mode. note 1: the pspif, pspie and pspip bits are reserved on 28-pin devices; always maintain these bits clear.
pic16f87xa ds39582b-page 80 ? 2003 microchip technology inc. 9.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (scl) ? rc3/sck/scl serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs or outputs through the trisc<4:3> bits. figure 9-7: mssp block diagram (i 2 c mode) 9.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register (sspcon) mssp control register 2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) ? not directly accessible mssp address register (sspadd) sspcon, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon and sspcon2 registers are readable and writable. the lower six bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the ssp is configured in i 2 c slave mode. when the ssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/sdi/ shift clock msb lsb sda
? 2003 microchip technology inc. ds39582b-page 81 pic16f87xa register 9-3: sspstat: mssp status register (i 2 c mode) (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 3 s: start bit 1 = indicates that a start bit has been detected last 0 = start bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 2 r/w : read/write bit information (i 2 c mode only) in slave mode: 1 = read 0 = write note: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in master mode: 1 = transmit is in progress 0 = transmit is not in progress note: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty in receive mode: 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 82 ? 2003 microchip technology inc. register 9-4: sspcon1: mssp control register 1 (i 2 c mode) (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started. (must be cleared in software.) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word. (must be cleared in software.) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. (must be cleared in software.) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: synchronous serial port enable bit 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables the serial port and configures these pins as i/o port pins note: when enabled, the sda and scl pins must be properly configured as input or output. bit 4 ckp: sck release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address note: bit combinations not specifically listed here are either reserved or implemented in spi mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 83 pic16f87xa register 9-5: sspcon2: mssp control register 2 (i 2 c mode) (address 91h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) 1 = not acknowledge 0 = acknowledge note: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. bit 4 acken: acknowledge sequence enable bit (master receive mode only) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled/stretch enabled bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is enabled for slave transmit only (pic16f87x compatibility) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled).
pic16f87xa ds39582b-page 84 ? 2003 microchip technology inc. 9.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspcon<5>). the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = osc/4 (sspadd + 1) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open-drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 9.4.3 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit, bf (sspstat<0>), was set before the transfer was received. the overflow bit, sspov (sspcon<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter #100 and parameter #101. 9.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incom- ing bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is com- pared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. mssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif.
? 2003 microchip technology inc. ds39582b-page 85 pic16f87xa 9.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an mssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon<0> = 1 ), rc3/sck/scl will be held low (clock stretch) following each data trans- fer. the clock must be released by setting bit ckp (sspcon<4>). see section 9.4.4 ?clock stretching? for more detail. 9.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low regard- less of sen (see section 9.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp (sspcon<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 9-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is com- plete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat regis- ter) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3/sck/scl must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse.
pic16f87xa ds39582b-page 86 ? 2003 microchip technology inc. figure 9-8: i 2 c slave mode timing with sen = 0 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon<6>) s 1 2 34 56 7 8 91 234 5 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp (ckp does not reset to ? 0 ? when sen = 0 )
? 2003 microchip technology inc. ds39582b-page 87 pic16f87xa figure 9-9: i 2 c slave mode timing (transmission, 7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software scl held low while cpu responds to sspif from sspif isr data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software
pic16f87xa ds39582b-page 88 ? 2003 microchip technology inc. figure 9-10: i 2 c slave mode timing with sen = 0 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 567 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place
? 2003 microchip technology inc. ds39582b-page 89 pic16f87xa figure 9-11: i 2 c slave mode timing (transmission, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 111 0a9a8 a7 a6a5a4a3a2a1a0 11110 a8 r/w=1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon<4>) ckp is set in software ckp is automatically cleared in hardware holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? bf flag is clear third address sequence at the end of the
pic16f87xa ds39582b-page 90 ? 2003 microchip technology inc. 9.4.4 clock stretching both 7 and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 9.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence, if the bf bit is set, the ckp bit in the sspcon register is automatically cleared, forcing the scl output to be held low. the ckp bit being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 9-13). 9.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode, during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address, with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 9.4.4.3 clock stretching for 7-bit slave transmit mode 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock, if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 9-9). 9.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is con- trolled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence, which contains the high order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 9-11). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching, on the basis of the state of the bf bit, only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit.
? 2003 microchip technology inc. ds39582b-page 91 pic16f87xa 9.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the scl output is forced to ? 0 ?; however, setting the ckp bit will not assert the scl output low until the scl output is already sampled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 9-12). figure 9-12: clock synchronization timing sda scl dx-1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon ckp master device deasserts clock master device asserts clock
pic16f87xa ds39582b-page 92 ? 2003 microchip technology inc. figure 9-13: i 2 c slave mode timing with sen = 1 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon<6>) s 1 234 56 7 8 9 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs
? 2003 microchip technology inc. ds39582b-page 93 pic16f87xa figure 9-14: i 2 c slave mode timing sen = 1 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6 a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua, and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1
pic16f87xa ds39582b-page 94 ? 2003 microchip technology inc. 9.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 9-15). figure 9-15: slave mode general call address sequence (7 or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address. gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt. ? 0 ? ? 1 ?
? 2003 microchip technology inc. ds39582b-page 95 pic16f87xa 9.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register, initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 9-16: mssp block diagram (i 2 c master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condi- tion is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, start bit detect sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0
pic16f87xa ds39582b-page 96 ? 2003 microchip technology inc. 9.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode opera- tion is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 9.4.7 ?baud rate generator? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete.
? 2003 microchip technology inc. ds39582b-page 97 pic16f87xa 9.4.7 baud rate generator in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 9-17). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 9-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. figure 9-17: baud rate generator block diagram table 9-3: i 2 c clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload f cy f cy * 2 brg value f scl (2 rollovers of brg) 10 mhz 20 mhz 19h 400 khz (1) 10 mhz 20 mhz 20h 312.5 khz 10 mhz 20 mhz 3fh 100 khz 4 mhz 8 mhz 0ah 400 khz (1) 4 mhz 8 mhz 0dh 308 khz 4 mhz 8 mhz 28h 100 khz 1 mhz 2 mhz 03h 333 khz (1) 1 mhz 2 mhz 0ah 100 khz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application.
pic16f87xa ds39582b-page 98 ? 2003 microchip technology inc. 9.4.7.1 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count, in the event that the clock is held low by an external device (figure 9-17). figure 9-18: baud rate generator timing wi th clock arbitration sda scl scl deasserted but slave holds dx-1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles
? 2003 microchip technology inc. ds39582b-page 99 pic16f87xa 9.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start con- dition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low, while scl is high, is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the con- tents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hard- ware, the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 9.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 9-19: first start bit timing note: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag (bclif) is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
pic16f87xa ds39582b-page 100 ? 2003 microchip technology inc. 9.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sam- pled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate genera- tor times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 9.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 9-20: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low to high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here, t brg t brg t brg and sets sspif
? 2003 microchip technology inc. ds39582b-page 101 pic16f87xa 9.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification, parameter #106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification, parameter #107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurred or if data was received prop- erly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 9-21). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl, until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 9.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all eight bits are shifted out. 9.4.10.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 9.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data. 9.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high to low/ low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automat- ically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 9.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 9.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 9.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic16f87xa ds39582b-page 102 ? 2003 microchip technology inc. figure 9-21: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w . start transmit. scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 2003 microchip technology inc. ds39582b-page 103 pic16f87xa figure 9-22: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence, sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence, sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
pic16f87xa ds39582b-page 104 ? 2003 microchip technology inc. 9.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 9-23). 9.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 9.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sam- pled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 9-24). 9.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 9-23: acknowledge sequence waveform figure 9-24: stop condition receiv e or transmit mode note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software ack scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
? 2003 microchip technology inc. ds39582b-page 105 pic16f87xa 9.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or com- plete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 9.4.15 effect of a reset a reset disables the mssp module and terminates the current transfer. 9.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is at the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 9.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state (figure 9-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the con- dition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determi- nation of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register or the bus is idle and the s and p bits are cleared. figure 9-25: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven set bus collision interrupt (bclif) by the master. bus collision has occurred. by master data changes while scl = 0
pic16f87xa ds39582b-page 106 ? 2003 microchip technology inc. 9.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 9-26). b) scl is sampled low before sda is asserted low (figure 9-27). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted, the bclif flag is set and the mssp module is reset to its idle state (figure 9-26). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 9-28). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0 and during this time, if the scl pin is sampled as ? 0 ?, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 9-26: bus collision during st art condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address fol- lowing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif. s
? 2003 microchip technology inc. ds39582b-page 107 pic16f87xa figure 9-27: bus collision duri ng start condition (scl = 0 ) figure 9-28: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1
pic16f87xa ds39582b-page 108 ? 2003 microchip technology inc. 9.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, see figure 9-29). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high to low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (figure 9-30). if at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 9-29: bus collision during a repeated start condition (case 1) figure 9-30: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
? 2003 microchip technology inc. ds39582b-page 109 pic16f87xa 9.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 9-31). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 9-32). figure 9-31: bus collision during a stop condition (case 1) figure 9-32: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
pic16f87xa ds39582b-page 110 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 111 pic16f87xa 10.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial communications interface or sci.) the usart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full-duplex) synchronous ? master (half-duplex) synchronous ? slave (half-duplex) bit spen (rcsta<7>) and bits trisc<7:6> have to be set in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchronous receiver transmitter. the usart module also has a multi-processor communication capability using 9-bit address detection. register 10-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data, can be parity bit legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 112 ? 2003 microchip technology inc. register 10-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode: don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ): 1 = enables address detection, enables interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data (can be parity bit but must be calculated by user firmware) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39582b-page 113 pic16f87xa 10.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 10-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 10-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1 ) even for slower baud clocks. this is because the f osc /(16 (x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 10.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 10-1: baud rate formula table 10-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64 (x + 1)) (synchronous) baud rate = f osc /(4 (x + 1)) baud rate = f osc /(16 (x + 1)) n/a legend: x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used by the brg.
pic16f87xa ds39582b-page 114 ? 2003 microchip technology inc. table 10-3: baud rates for asynchronous mode (brgh = 0 ) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3------- -- 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 high 1.221 - 255 0.977 - 255 0.610 - 255 low 312.500 - 0 250.000 - 0 156.250 - 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 0.17 51 1.2 0 47 2.4 2.404 0.17 25 2.4 0 23 9.6 8.929 6.99 6 9.6 0 5 19.2 20.833 8.51 2 19.2 0 2 28.8 31.250 8.51 1 28.8 0 1 33.6 - - - - - - 57.6 62.500 8.51 0 57.6 0 0 high 0.244 - 255 0.225 - 255 low 62.500 - 0 57.6 - 0 table 10-4: baud rates for asynchronous mode (brgh = 1 ) baud rate (k) f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3--------- 1.2--------- 2.4 - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 high 4.883 - 255 3.906 - 255 2.441 - 255 low 1250.000 - 0 1000.000 0 625.000 - 0 baud rate (k) f osc = 4 mhz f osc = 3.6864 mhz kbaud % error spbrg value (decimal) kbaud % error spbrg value (decimal) 0.3------ 1.2 1.202 0.17 207 1.2 0 191 2.4 2.404 0.17 103 2.4 0 95 9.6 9.615 0.16 25 9.6 0 23 19.2 19.231 0.16 12 19.2 0 11 28.8 27.798 3.55 8 28.8 0 7 33.6 35.714 6.29 6 32.9 2.04 6 57.6 62.500 8.51 3 57.6 0 3 high 0.977 - 255 0.9 - 255 low 250.000 - 0 230.4 - 0
? 2003 microchip technology inc. ds39582b-page 115 pic16f87xa 10.2 usart asynchronous mode in this mode, the usart uses standard non-return- to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 10.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 10-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit, txif (pir1<4>), is set. this interrupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. status bit trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit, txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 10-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 10-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rc6/tx/ck pin will revert to high-impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. figure 10-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ?
pic16f87xa ds39582b-page 116 ? 2003 microchip technology inc. when setting up an asynchronous transmission, follow these steps: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. figure 10-2: asynchronous master transmission figure 10-3: asynchronous master transmission (back to back) table 10-5: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows tw o consecutive transmissions.
? 2003 microchip technology inc. ds39582b-page 117 pic16f87xa 10.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 10-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift register (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, flag bit, rcif (pir1<5>), is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit, rcie (pie1<5>). flag bit rcif is a read-only bit which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double-buffered register (i.e., it is a two-deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, the overrun error bit, oerr (rcsta<1>), will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in soft- ware. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhib- ited and no further data will be received. it is, therefore, essential to clear error bit oerr if it is set. framing error bit, ferr (rcsta<2>), is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load bits rx9d and ferr with new values, therefore, it is essential for the user to read the rcsta register before reading the rcreg register in order not to lose the old ferr and rx9d information. figure 10-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? f osc
pic16f87xa ds39582b-page 118 ? 2003 microchip technology inc. figure 10-5: asynchronous reception when setting up an asynchronous reception, follow these steps: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie is set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 10-6: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun error) bit to be set. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39582b-page 119 pic16f87xa 10.2.3 setting up 9-bit mode with address detect when setting up an asynchronous reception with address detect enabled: initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh. enable the asynchronous serial port by clearing bit sync and setting bit spen. if interrupts are desired, then set enable bit rcie. set bit rx9 to enable 9-bit reception. set adden to enable address detect. enable the reception by setting enable bit cren. flag bit rcif will be set when reception is complete, and an interrupt will be generated if enable bit rcie was set. read the rcsta register to get the ninth bit and determine if any error occurred during reception. read the 8-bit received data by reading the rcreg register to determine if the device is being addressed. if any error occurred, clear the error by clearing enable bit cren. if the device has been addressed, clear the adden bit to allow data bytes and address bytes to be read into the receive buffer and interrupt the cpu. figure 10-6: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? rx9 adden rx9 adden rsr<8> enable load of receive buffer 8 8 f osc
pic16f87xa ds39582b-page 120 ? 2003 microchip technology inc. figure 10-7: asynchronous reception with address detect figure 10-8: asynchronous reception with address byte first table 10-7: registers associated with asynchronous reception start bit bit 1 bit 0 bit 8 bit 0 stop bit start bit bit 8 stop bit rc7/rx/dt load rsr read rcif word 1 rcreg bit 8 = 0 , data byte bit 8 = 1 , address byte note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive buffer) because adden = 1 . (pin) start bit bit 1 bit 0 bit 8 bit 0 stop bit start bit bit 8 stop bit rc7/rx/dt load rsr read rcif word 1 rcreg bit 8 = 1 , address byte bit 8 = 0 , data byte note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive buffer) because adden was not updated and still = 0 . (pin) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39582b-page 121 pic16f87xa 10.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta<4>). in addition, enable bit, spen (rcsta<7>), is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit, csrc (txsta<7>). 10.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 10-6. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt bit, txif (pir1<4>), is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. trmt is a read- only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. transmission is enabled by setting enable bit, txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is stable around the falling edge of the synchronous clock (figure 10-9). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 10-10). this is advantageous when slow baud rates are selected since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty so a transfer to the txreg register will result in an immediate transfer to tsr, resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to high- impedance. if either bit cren or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a high-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting since bit txen is still set. the dt line will immediately switch from high- impedance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?new? tx9d, the ?present? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set.
pic16f87xa ds39582b-page 122 ? 2003 microchip technology inc. table 10-8: registers associated with synchronous master transmission figure 10-9: synchronous transmission figure 10-10: synchronous tr ansmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode; spbrg = 0 . continuous transmission of two 8-bit words. pin pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
? 2003 microchip technology inc. ds39582b-page 123 pic16f87xa 10.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit, sren (rcsta<5>), or enable bit, cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the recep- tion is continuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit, rcif (pir1<5>), is set. the actual interrupt can be enabled/ disabled by setting/clearing enable bit, rcie (pie1<5>). flag bit rcif is a read-only bit which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double-buffered register (i.e., it is a two- deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit, oerr (rcsta<1>), is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited so it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. reading the rcreg register will load bit rx9d with a new value, therefore, it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old rx9d information. when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate ( section 10.1 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 10-9: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear.
pic16f87xa ds39582b-page 124 ? 2003 microchip technology inc. figure 10-11: synchronous rece ption (master mode, sren) 10.4 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit, csrc (txsta<7>). 10.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). when setting up a synchronous slave transmission, follow these steps: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. cren bit rc7/rx/dt rc6/tx/ck write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brg = 0 . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 pin pin
? 2003 microchip technology inc. ds39582b-page 125 pic16f87xa table 10-10: registers associated with synchronous slave transmission 10.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. bit sren is a ?don't care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr reg- ister will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). when setting up a synchronous slave reception, follow these steps: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that gie and peie (bits 7 and 6) of the intcon register are set. table 10-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on 28-pin devices; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf r0if 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on 28-pin devices, always maintain these bits clear.
pic16f87xa ds39582b-page 126 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 127 pic16f87xa 11.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has five inputs for the 28-pin devices and eight for the 40/44-pin devices. the conversion of an analog input signal results in a corresponding 10-bit digital number. the a/d module has high and low-voltage reference input that is soft- ware selectable to some combination of v dd , v ss , ra2 or ra3. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d clock must be derived from the a/d?s internal rc oscillator. the a/d module has four regi sters. these registers are: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) the adcon0 register, shown in register 11-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 11-2, configures the func- tions of the port pins. the port pins can be configured as analog inputs (ra3 can also be the voltage reference) or as digital i/o. additional information on using the a/d module can be found in the picmicro ? mid-range mcu family reference manual (ds33023). register 11-1: adcon0 register (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon bit 7 bit 0 bit 7-6 adcs1:adcs0: a/d conversion clock select bits (adcon0 bits in bold ) bit 5-3 chs2:chs0: analog channel select bits 000 = channel 0 (an0) 001 = channel 1 (an1) 010 = channel 2 (an2) 011 = channel 3 (an3) 100 = channel 4 (an4) 101 = channel 5 (an5) 110 = channel 6 (an6) 111 = channel 7 (an7) note: the pic16f873a/876a devices only implement a/d channels 0 through 4; the unimplemented selections are reserved. do not select any unimplemented channels with these devices. bit 2 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress (setting this bit starts the a/d conversion which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1 unimplemented: read as ? 0 ? bit 0 adon: a/d on bit 1 = a/d converter module is powered up 0 = a/d converter module is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown adcon1 adcon0 clock conversion 0 00 f osc /2 0 01 f osc /8 0 10 f osc /32 0 11 f rc (clock derived from the in ternal a/d rc oscillator) 1 00 f osc /4 1 01 f osc /16 1 10 f osc /64 1 11 f rc (clock derived from the in ternal a/d rc oscillator)
pic16f87xa ds39582b-page 128 ? 2003 microchip technology inc. register 11-2: adcon1 register (address 9fh) r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified. six (6) most significant bits of adresh are read as ? 0 ?. 0 = left justified. six (6) least significant bits of adresl are read as ? 0 ?. bit 6 adcs2: a/d conversion clock select bit (adcon1 bits in shaded area and in bold ) bit 5-4 unimplemented: read as ? 0 ? bit 3-0 pcfg3:pcfg0: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: on any device reset, the port pins that are multiplexed with analog functions (anx) are forced to be an analog input. adcon1 adcon0 clock conversion 0 00 f osc /2 0 01 f osc /8 0 10 f osc /32 0 11 f rc (clock derived from the internal a/d rc oscillator) 1 00 f osc /4 1 01 f osc /16 1 10 f osc /64 1 11 f rc (clock derived from the internal a/d rc oscillator) a = analog input d = digital i/o c/r = # of analog input channels/# of a/d voltage references pcfg <3:0> an7 an6 an5 an4 an3 an2 an1 an0 v ref +v ref -c/r 0000 aaaa a a aav dd v ss 8/0 0001 aaaav ref +a a aan3v ss 7/1 0010 ddda a a aav dd v ss 5/0 0011 dddav ref +a a aan3v ss 4/1 0100 dddd a d aav dd v ss 3/0 0101 ddddv ref +d a aan3v ss 2/1 011x dddd d d dd ? ?0/0 1000 aaaav ref +v ref -a a an3an26/2 1001 ddaa a a aav dd v ss 6/0 1010 ddaav ref +a a aan3v ss 5/1 1011 ddaav ref +v ref -a a an3an24/2 1100 dddav ref +v ref -a a an3an23/2 1101 ddddv ref +v ref -a a an3an22/2 1110 dddd d d dav dd v ss 1/0 1111 ddddv ref +v ref -d a an3an21/2
? 2003 microchip technology inc. ds39582b-page 129 pic16f87xa the adresh:adresl registers contain the 10-bit result of the a/d conversion. when the a/d conversion is complete, the result is loaded into this a/d result register pair, the go/done bit (adcon0<2>) is cleared and the a/d interrupt flag bit adif is set. the block diagram of the a/d module is shown in figure 11-1. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine sample time, see section 11.1 ?a/d acquisition requirements? . after this acquisition time has elapsed, the a/d conversion can be started. to do an a/d conversion, follow these steps: 1. configure the a/d module: configure analog pins/voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set peie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete by either: polling for the go/done bit to be cleared (interrupts disabled); or waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear bit adif if required. 7. for the next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . figure 11-1: a/d block diagram (input voltage) v ain v ref + (reference voltage) v dd pcfg3:pcfg0 chs2:chs0 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: not available on 28-pin devices. v ref - (reference voltage) v ss pcfg3:pcfg0
pic16f87xa ds39582b-page 130 ? 2003 microchip technology inc. 11.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 11-2. the source impedance (r s ) and the internal sampling switch impedance (r ss ) directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ); see figure 11-2. the maximum recommended impedance for analog sources is 2.5 k ? . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 11-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range mcu family reference manual (ds33023). equation 11-1: acquisition time figure 11-2: analog input model t acq t c t acq = = = = = = = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff 2 s + t c + [(temperature ? 25 c)(0.05 s/c)] c hold (r ic + r ss + r s ) in(1/2047) - 120 pf (1 k ? + 7 k ? + 10 k ? ) in(0.0004885) 16.47 s 2 s + 16.47 s + [(50c ? 25 c)(0.05 s/ c) 19.72 s note 1: the reference voltage (v ref ) has no effect on the equation since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 2.5 k ? . this is required to meet the pin leakage specification. c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 120 pf 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
? 2003 microchip technology inc. ds39582b-page 131 pic16f87xa 11.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires a minimum 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selected. the seven possible options for t ad are: 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal a/d module rc oscillator (2-6 s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 11-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 11.3 configuring analog port pins the adcon1 and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. table 11-1: t ad vs. maximum device operating frequencies (standard devices (f)) note 1: when reading the port register, any pin configured as an analog input channel will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally config- ured input will not affect the conversion accuracy. 2: analog levels on any pin that is defined as a digital input (including the an7:an0 pins) may cause the input buffer to con- sume current that is out of the device specifications. ad clock source (t ad ) maximum device frequency operation adcs2:adcs1:adcs0 2 t osc 000 1.25 mhz 4 t osc 100 2.5 mhz 8 t osc 001 5 mhz 16 t osc 101 10 mhz 32 t osc 010 20 mhz 64 t osc 110 20 mhz rc (1, 2, 3) x11 (note 1) note 1: the rc source has a typical t ad time of 4 s but can vary between 2-6 s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. 3: for extended voltage devices (lf), please refer to section 17.0 ?electrical characteristics? .
pic16f87xa ds39582b-page 132 ? 2003 microchip technology inc. 11.4 a/d conversions clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, the next acquisition on the selected channel is automatically started. the go/done bit can then be set to start the conversion. in figure 11-3, after the go bit is set, the first time segment has a minimum of t cy and a maximum of t ad . figure 11-3: a/d conversion t ad cycles 11.4.1 a/d result registers the adresh:adresl register pair is the location where the 10-bit a/d result is loaded at the completion of the a/d conversion. this register pair is 16 bits wide. the a/d module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. the a/d format select bit (adfm) controls this justification. figure 11-4 shows the operation of the a/d result justification. the extra bits are loaded with ? 0 ?s. when an a/d result will not overwrite these locations (a/d dis- able), these registers may be used as two general purpose 8-bit registers. figure 11-4: a/d result justification note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go bit holding capacitor is disconnected fr om analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 10 t ad 11 b1 b0 t cy to t ad conversion starts adres is loaded go bit is cleared adif bit is set holding capacitor is connected to analog input 10-bit result adresh adresl 0000 00 adfm = 0 0 2 1 0 7 7 10-bit result adresh adresl 10-bit result 0000 00 7 0 7 6 5 0 adfm = 1 right justified left justified
? 2003 microchip technology inc. ds39582b-page 133 pic16f87xa 11.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 11.6 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. all a/d input pins are configured as analog inputs. the value that is in the adresh:adresl registers is not modified for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. table 11-2: registers/bits associated with a/d note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to allow the con- version to occur during sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on mclr , wdt 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 1eh adresh a/d result register high byte xxxx xxxx uuuu uuuu 9eh adresl a/d result register low byte xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 0000 00-0 9fh adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 00-- 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 05h porta ? ? porta data latch when written: porta pins when read --0x 0000 --0u 0000 89h (1) trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 09h (1) porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: these registers are not av ailable on 28-pin devices.
pic16f87xa ds39582b-page 134 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 135 pic16f87xa 12.0 comparator module the comparator module contains two analog compara- tors. the inputs to the comparators are multiplexed with i/o port pins ra0 through ra3, while the outputs are multiplexed to pins ra4 and ra5. the on-chip volt- age reference ( section 13.0 ?comparator voltage reference module? ) can also be an input to the comparators. the cmcon register (register 12-1) controls the com- parator input and output multiplexers. a block diagram of the various comparator configurations is shown in figure 12-1. register 12-1: cmcon register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to ra3/an3 c2 v in - connects to ra2/an2 0 =c1 v in - connects to ra0/an0 c2 v in - connects to ra1/an1 bit 2 cm2:cm0 : comparator mode bits figure 12-1 shows the comparator modes and cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 136 ? 2003 microchip technology inc. 12.1 comparator configuration there are eight modes of operation for the compara- tors. the cmcon register is used to select these modes. figure 12-1 shows the eight possible modes. the trisa register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 17.0 ?electrical characteristics? . figure 12-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change. otherwise, a false interrupt may occur. c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) comparators reset a a cm2:cm0 = 000 c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) a a c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators a a cm2:cm0 = 010 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators a a cm2:cm0 = 100 c2 ra1/an1 v in - v in + ra2/an2 c2out a d c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 ra0/an0 v in - v in + ra3/an3 c1out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as ? 0 ?) comparators off (por default value) d d cm2:cm0 = 111 c2 ra1/an1 v in - v in + ra2/an2 off (read as ? 0 ?) d d c1 ra0/an0 v in - v in + ra3/an3 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 ra1/an1 v in - v in + ra2/an2 c2out a a from comparator cis = 0 cis = 1 cis = 0 cis = 1 c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 ra1/an1 v in - v in + ra2/an2 c2out a d a = analog input, port reads zeros always. d = digital i nput. cis (cmcon<3>) is the comparator input switch. cv ref c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 ra1/an1 v in - v in + ra2/an2 c2out a a ra4/t0cki/c1out ra5/an4/ss /c2out ra4/t0cki/c1out ra5/an4/ss /c2out ra4/t0cki/c1out v ref module
? 2003 microchip technology inc. ds39582b-page 137 pic16f87xa 12.2 comparator operation a single comparator is shown in figure 12-2 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 12-2 represent the uncertainty due to input offsets and response time. 12.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 12-2). figure 12-2: single comparator 12.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 12.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the compara- tors. section 13.0 ?comparator voltage reference module? contains a detailed description of the compar- ator voltage reference module that provides this signal. the internal reference signal is used when comparators are in mode, cm<2:0> = 110 (figure 12-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 12.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the com- parator output has a valid level. if the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the compar- ator outputs. otherwise, the maximum delay of the comparators should be used ( section 17.0 ?electrical characteristics? ). 12.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the ra4 and ra5 i/o pins. when enabled, multiplexors in the output path of the ra4 and ra5 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 12-3 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the ra4 and ra5 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). ? + v in + v in - output v in? v in+ o utput output v in + v in - note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a dig- ital input may cause the input buffer to consume more current than is specified. 3: ra4 is an open collector i/o pin. when used as an output, a pull-up resistor is required.
pic16f87xa ds39582b-page 138 ? 2003 microchip technology inc. figure 12-3: comparator output block diagram 12.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir registers) is the comparator interrupt flag. the cmif bit must be reset by clearing it (? 0 ?). since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cmie bit (pie registers) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. d q en to ra4 or ra5 pin bus data read cmcon set multiplex cmif bit - + d q en cl port pins read cmcon reset from other comparator cxinv note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir registers) interrupt flag may not get set.
? 2003 microchip technology inc. ds39582b-page 139 pic16f87xa 12.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current as shown in the com- parator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111, before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 12.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator off mode, cm<2:0> = 111 . this ensures compatibility to the pic16f87x devices. 12.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 12-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is rec- ommended for the analog sources. any external com- ponent connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 12-4: analog input model va r s < 10k a in c pin 5 pf v dd v t = 0.6 v v t = 0.6 v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage
pic16f87xa ds39582b-page 140 ? 2003 microchip technology inc. table 12-1: registers associated with comparator module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 0bh, 8bh, 10bh,18bh intcon gie/ gieh peie/ giel tmr0ie intie rbie tmr0if intif rbif 0000 000x 0000 000u 0dh pir2 ?cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 8dh pie2 ?cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module.
? 2003 microchip technology inc. ds39582b-page 141 pic16f87xa 13.0 comparator voltage reference module the comparator voltage reference generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ? 110 ? . a programmable register controls the function of the reference generator. register 13-1 lists the bit functions of the cvrcon register. as shown in figure 13-1, the resistor ladder is seg- mented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the comparator reference supply voltage (also referred to as cv rsrc ) comes directly from v dd . it should be noted, however, that the voltage at the top of the ladder is cv rsrc ? v sat , where v sat is the saturation voltage of the power switch transistor. this reference will only be as accurate as the values of cv rsrc and v sat . the output of the reference generator may be con- nected to the ra2/an2/v ref -/cv ref pin. this can be used as a simple d/a function by the user if a very high- impedance load is used. the primary purpose of this function is to provide a test path for testing the reference generator function. register 13-1: cvrcon control register (address 9dh) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe: comparator v ref output enable bit 1 =cv ref voltage level is output on ra2/an2/v ref -/cv ref pin 0 =cv ref voltage level is disconnected from ra2/an2/v ref -/cv ref pin bit 5 cvrr : comparator v ref range selection bit 1 = 0 to 0.75 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 unimplemented: read as ? 0 ? bit 3-0 cvr3:cvr0: comparator v ref value selection bits 0 vr3:vr0 15 when cvrr = 1 : cv ref = (vr<3:0>/ 24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (vr3:vr0/ 32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16f87xa ds39582b-page 142 ? 2003 microchip technology inc. figure 13-1: comparator voltage reference block diagram table 13-1: registers associated with comparator voltage reference cvrr 8r cvr3 cvr0 16:1 analog mux 8r r r r r cvren cv ref 16 stages input to comparator cvroe ra2/an2/v ref -/cv ref v dd cvr2 cvr1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 9dh cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 9ch cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference.
? 2003 microchip technology inc. ds39582b-page 143 pic16f87xa 14.0 special features of the cpu all pic16f87xa devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming low-voltage in-circuit serial programming in-circuit debugger pic16f87xa devices have a watchdog timer which can be shut-off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscil- lator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits is used to select various options. additional information on special features is available in the picmicro ? mid-range mcu family reference manual (ds33023). 14.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?) to select various device configurations. the erased or unprogrammed value of the configuration word register is 3fffh. these bits are mapped in program memory location 2007h. it is important to note that address 2007h is beyond the user program memory space which can be accessed only during programming.
pic16f87xa ds39582b-page 144 ? 2003 microchip technology inc. register 14-1: configurat ion word (address 2007h) (1) r/p-1 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 cp ? debug wrt1 wrt0 cpd lvp boren ? ?pwrten wdten f osc 1f osc 0 bit 13 bit0 bit 13 cp: flash program memory code protection bit 1 = code protection off 0 = all program memory code-protected bit 12 unimplemented: read as ? 1 ? bit 11 debug: in-circuit debugger mode bit 1 = in-circuit debugger disabled, rb6 and rb7 are general purpose i/o pins 0 = in-circuit debugger enabled, rb6 and rb7 are dedicated to the debugger bit 10-9 wrt1:wrt0 flash program memory write enable bits for pic16f876a/877a: 11 = write protection off; all program memory may be written to by eecon control 10 = 0000h to 00ffh write-protected; 0100h to 1fffh may be written to by eecon control 01 = 0000h to 07ffh write-protected; 0800h to 1fffh may be written to by eecon control 00 = 0000h to 0fffh write-protected; 1000h to 1fffh may be written to by eecon control for pic16f873a/874a: 11 = write protection off; all program memory may be written to by eecon control 10 = 0000h to 00ffh write-protected; 0100h to 0fffh may be written to by eecon control 01 = 0000h to 03ffh write-protected; 0400h to 0fffh may be written to by eecon control 00 = 0000h to 07ffh write-protected; 0800h to 0fffh may be written to by eecon control bit 8 cpd: data eeprom memory code protection bit 1 = data eeprom code protection off 0 = data eeprom code-protected bit 7 lvp : low-voltage (single-supply) in-circuit serial programming enable bit 1 = rb3/pgm pin has pgm function; low-voltage programming enabled 0 = rb3 is digital i/o, hv on mclr must be used for programming bit 6 boren : brown-out reset enable bit 1 = bor enabled 0 = bor disabled bit 5-4 unimplemented: read as ? 1 ? bit 3 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 2 wdten : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 f osc 1:f osc 0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state note 1: the erased (unprogrammed) value of the configuration word is 3fffh.
? 2003 microchip technology inc. ds39582b-page 145 pic16f87xa 14.2 oscillator configurations 14.2.1 oscillator types the pic16f87xa can be operated in four different oscillator modes. the user can program two configura- tion bits (f osc 1 and f osc 0) to select one of these four modes: lp low-power crystal xt crystal/resonator hs high-speed crystal/resonator rc resistor/capacitor 14.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clki and osc2/clko pins to establish oscillation (figure 14-1). the pic16f87xa oscillator design requires the use of a parallel cut crys- tal. use of a series cut crystal may give a frequency out of the crystal manufacturer?s specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/clki pin (figure 14-2). figure 14-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 14-2: external clock input operation (hs, xt or lp osc configuration) table 14-1: ceramic resonators note 1: see table 14-1 and table 14-2 for recommended values of c1 and c2. 2: a series resistor ( r s ) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16f87xa r s (2) internal ranges tested: mode freq. osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-68 pf 15-68 pf 68-100 pf 15-68 pf 15-68 pf hs 8.0 mhz 16.0 mhz 10-68 pf 10-22 pf 10-68 pf 10-22 pf these values are for design guidance only. see notes following table 14-2. resonators used: 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. osc1 osc2 open clock from ext. system pic16f87xa
pic16f87xa ds39582b-page 146 ? 2003 microchip technology inc. table 14-2: capacitor selection for crystal oscillator 14.2.3 rc oscillator for timing insensitive applications, the ?rc? device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 14-3 shows how the r/c combination is connected to the pic16f87xa. figure 14-3: rc oscillator mode osc type crystal freq. cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes following this table. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: r s may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: when migrating from other picmicro ? devices, oscillator performance should be verified. osc2/clko c ext r ext pic16f87xa osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf
? 2003 microchip technology inc. ds39582b-page 147 pic16f87xa 14.3 reset the pic16f87xa differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (during normal operation) wdt wake-up (during sleep) brown-out reset (bor) some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep and brown- out reset (bor). they are not affected by a wdt wake-up which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differ- ently in different reset situations as indicated in table 14-4. these bits are used in software to deter- mine the nature of the reset. see table 14-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 14-4. figure 14-4: simplified block diagram of on-chip reset circuit s rq external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. brown-out reset boden (1)
pic16f87xa ds39582b-page 148 ? 2003 microchip technology inc. 14.4 mclr pic16f87xa devices have a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin differs from previous devices of this family. voltages applied to the pin that exceed its specification can result in both resets and current consumption outside of device specification during the reset event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rcr network, as shown in figure 14-5, is suggested. figure 14-5: recommended mclr circuit 14.5 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v-1.7v). to take advantage of the por, tie the mclr pin to v dd through an rc network, as described in section 14.4 ?mclr? . a maximum rise time for v dd is specified. see section 17.0 ?electrical characteristics? for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating condi- tions are met. brown-out reset may be used to meet the start-up conditions. for additional information, refer to application note, an607, ? power-up trouble shooting ? (ds00607). 14.6 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up only from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt?s time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable or disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see section 17.0 ?electrical characteristics? for details (t pwrt , parameter #33). 14.7 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a delay of 1024 oscillator cycles (from osc1 input) after the pwrt delay is over (if pwrt is enabled). this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 14.8 brown-out reset (bor) the configuration bit, boden, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72 ms). if v dd should fall below v bor during t pwrt , the brown-out reset process will restart when v dd rises above v bor with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the pwrt configuration bit. 14.9 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por reset occurs. then, ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution immediately. this is useful for testing purposes or to synchronize more than one pic16f87xa device operating in parallel. table 14-5 shows the reset conditions for the status, pcon and pc registers, while table 14-6 shows the reset conditions for all the registers. c1 r1 (1) v dd mclr pic16f87xa r2 (2) note 1: r1 < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 2: r2 > than 1k will limit any current flowing into mclr from the external capacitor c, in the event of mclr /v pp breakdown due to electrostatic discharge (esd) or electrical overstress (eos).
? 2003 microchip technology inc. ds39582b-page 149 pic16f87xa 14.10 power control/status register (pcon) the power control/status register, pcon, has up to two bits depending upon the device. bit 0 is the brown-out reset status bit, bor . the bor bit is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if it has been cleared, indicating that a bor has occurred. when the brown-out reset is disabled, the state of the bor bit is unpredictable and is, therefore, not valid at any time. bit 1 is the power-on reset status bit, por . it is cleared on a power-on reset and unaffected other- wise. the user must set this bit following a power-on reset. table 14-3: time-out in various situations table 14-4: status bits and their significance table 14-5: reset conditions for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms ? 72 ms ? por bor to pd condition 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep legend: x = don?t care, u = unchanged condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16f87xa ds39582b-page 150 ? 2003 microchip technology inc. table 14-6: initialization conditions for all registers register devices power-on reset, brown-out reset mclr resets, wdt reset wake-up via wdt or interrupt w 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu indf 73a 74a 76a 77a n/a n/a n/a tmr0 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu pcl 73a 74a 76a 77a 0000 0000 0000 0000 pc + 1 (2) status 73a 74a 76a 77a 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu porta 73a 74a 76a 77a --0x 0000 --0u 0000 --uu uuuu portb 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu portc 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu portd 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu porte 73a 74a 76a 77a ---- -xxx ---- -uuu ---- -uuu pclath 73a 74a 76a 77a ---0 0000 ---0 0000 ---u uuuu intcon 73a 74a 76a 77a 0000 000x 0000 000u uuuu uuuu (1) pir1 73a 74a 76a 77a r000 0000 r000 0000 ruuu uuuu (1) 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu (1) pir2 73a 74a 76a 77a -0-0 0--0 -0-0 0--0 -u-u u--u (1) tmr1l 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu t1con 73a 74a 76a 77a --00 0000 --uu uuuu --uu uuuu tmr2 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu t2con 73a 74a 76a 77a -000 0000 -000 0000 -uuu uuuu sspbuf 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu sspcon 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu ccpr1l 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 73a 74a 76a 77a --00 0000 --00 0000 --uu uuuu rcsta 73a 74a 76a 77a 0000 000x 0000 000x uuuu uuuu txreg 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu rcreg 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu ccpr2l 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu adresh 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu adcon0 73a 74a 76a 77a 0000 00-0 0000 00-0 uuuu uu-u option_reg 73a 74a 76a 77a 1111 1111 1111 1111 uuuu uuuu trisa 73a 74a 76a 77a --11 1111 --11 1111 --uu uuuu trisb 73a 74a 76a 77a 1111 1111 1111 1111 uuuu uuuu trisc 73a 74a 76a 77a 1111 1111 1111 1111 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 14-5 for reset value for specific condition.
? 2003 microchip technology inc. ds39582b-page 151 pic16f87xa figure 14-6: time-out sequence on power-up (mclr tied to v dd via rc network) trisd 73a 74a 76a 77a 1111 1111 1111 1111 uuuu uuuu trise 73a 74a 76a 77a 0000 -111 0000 -111 uuuu -uuu pie1 73a 74a 76a 77a r000 0000 r000 0000 ruuu uuuu 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu pie2 73a 74a 76a 77a -0-0 0--0 -0-0 0--0 -u-u u--u pcon 73a 74a 76a 77a ---- --qq ---- --uu ---- --uu sspcon2 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu pr2 73a 74a 76a 77a 1111 1111 1111 1111 1111 1111 sspadd 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu sspstat 73a 74a 76a 77a --00 0000 --00 0000 --uu uuuu txsta 73a 74a 76a 77a 0000 -010 0000 -010 uuuu -uuu spbrg 73a 74a 76a 77a 0000 0000 0000 0000 uuuu uuuu cmcon 73a 974 76a 77a 0000 0111 0000 0111 uuuu uuuu cvrcon 73a 74a 76a 77a 000- 0000 000- 0000 uuu- uuuu adresl 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu adcon1 73a 74a 76a 77a 00-- 0000 00-- 0000 uu-- uuuu eedata 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu eeadr 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu eedath 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu eeadrh 73a 74a 76a 77a xxxx xxxx uuuu uuuu uuuu uuuu eecon1 73a 74a 76a 77a x--- x000 u--- u000 u--- uuuu eecon2 73a 74a 76a 77a ---- ---- ---- ---- ---- ---- table 14-6: initialization conditions for all registers (continued) register devices power-on reset, brown-out reset mclr resets, wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition, r = reserved, maintain clear. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 14-5 for reset value for specific condition. t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16f87xa ds39582b-page 152 ? 2003 microchip technology inc. figure 14-7: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 14-8: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 14-9: slow rise time (mclr tied to v dd via rc network) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
? 2003 microchip technology inc. ds39582b-page 153 pic16f87xa 14.11 interrupts the pic16f87xa family has up to 15 sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts. when bit gie is enabled and an interrupt?s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be disabled through their corresponding enable bits in various registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?return from interrupt? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the special function registers, pir1 and pir2. the corresponding interrupt enable bits are contained in special function registers, pie1 and pie2, and the peripheral interrupt enable bit is contained in special function register, intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding mask bit, peie bit or gie bit. figure 14-10: interrupt logic note: individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the gie bit. pspif (1) pspie (1) adif adie rcif rcie txif txie sspif sspie tmr2if tmr2ie tmr1if tmr1ie tmr0if tmr0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if bclie bclif eeif eeie ccp1if ccp1ie cmie cmif note 1: psp interrupt is implemented only on pic16f874a/877a devices.
pic16f87xa ds39582b-page 154 ? 2003 microchip technology inc. 14.11.1 int interrupt external interrupt on the rb0/int pin is edge triggered, either rising if bit intedg (option_reg<6>) is set or falling if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit, intf (intcon<1>), is set. this interrupt can be disabled by clearing enable bit, inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep if bit inte was set prior to going into sleep. the status of global interrupt enable bit, gie, decides whether or not the processor branches to the interrupt vector following wake-up. see section 14.14 ?power-down mode (sleep)? for details on sleep mode. 14.11.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit, tmr0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). see section 5.0 ?timer0 module? . 14.11.3 portb intcon change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<4>). see section 4.2 ?portb and the trisb register? . 14.12 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w register and status register). this will have to be implemented in software. for the pic16f873a/874a devices, the register w_temp must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1). the regis- ters, pclath_temp and status_temp, are only defined in bank 0. since the upper 16 bytes of each bank are common in the pic16f876a/877a devices , temporary holding reg- isters, w_temp, status_temp and pclath_temp, should be placed in here. these 16 locations don?t require banking and therefore, make it easier for con- text save and restore. the same code shown in example 14-1 can be used. example 14-1: saving status, w and pclath registers in ram movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page : :(isr) ;(insert user code here) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2003 microchip technology inc. ds39582b-page 155 pic16f87xa 14.13 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clki pin. that means that the wdt will run even if the clock on the osc1/clki and osc2/clko pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit, wdte ( section 14.1 ?configuration bits? ). wdt time-out period values may be found in section 17.0 ?electrical characteristics? under parameter #31. values for the wdt prescaler (actually a postscaler but shared with the timer0 prescaler) may be assigned using the option_reg register. figure 14-11: watchdo g timer block diagram table 14-7: summary of watchdog timer registers note 1: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt and prevent it from timing out and generating a device reset condition. 2: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared but the prescaler assignment is not changed. from tmr0 clock source (figure 5-1) to tmr0 (figure 5-1) postscaler wdt timer wdt enable bit 0 1 m u x psa 8-to-1 mux ps2:ps0 0 1 mux psa wdt time-out 8 note: psa and ps2:ps0 are bits in the option_reg register. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boden (1) cp1 cp0 pwrte (1) wdte f osc 1 f osc 0 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 14-1 for operation of these bits.
pic16f87xa ds39582b-page 156 ? 2003 microchip technology inc. 14.14 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low or high-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external circuitry is drawing current from the i/o pin, power- down the a/d and disable external clocks. pull all i/o pins that are high-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). 14.14.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execu- tion and cause a ?wake-up?. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. psp read or write (pic16f874/877 only). 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. ccp capture mode interrupt. 4. special event trigger (timer1 in asynchronous mode using an external clock). 5. ssp (start/stop) bit detect interrupt. 6. ssp transmit or receive in slave mode (spi/i 2 c). 7. usart rx or tx (synchronous slave mode). 8. a/d conversion (when a/d clock source is rc). 9. eeprom write operation completion. 10. comparator output changes state. other peripherals cannot generate interrupts since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 14.14.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction.
? 2003 microchip technology inc. ds39582b-page 157 pic16f87xa figure 14-12: wake-up from sleep through interrupt 14.15 in-circuit debugger when the debug bit in the configuration word is pro- grammed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? icd. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 14-8 shows which features are consumed by the background debugger. table 14-8: debugger resources to use the in-circuit debugger function of the microcon- troller, the design must implement in-circuit serial pro- gramming connections to mclr /v pp , v dd , gnd, rb7 and rb6. this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. 14.16 program verification/code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 14.17 id locations four memory locations (2000h-2003h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. it is recommended that only the 4 least significant bits of the id location are used. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clko (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (drawing not to scale). this delay will not be there for rc oscillator mode. 3: gie = 1 assumed. in this case, after wake- up, the processor jumps to the interrupt routine. if gie = 0 , execution will continue in-line. 4: clko is not available in these oscillator modes but shown here for timing reference. i/o pins rb6, rb7 stack 1 level program memory address 0000h must be nop last 100h words data memory 0x070 (0x0f0, 0x170, 0x1f0) 0x1eb-0x1ef
pic16f87xa ds39582b-page 158 ? 2003 microchip technology inc. 14.18 in-circuit serial programming pic16f87xa microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. when using icsp, the part must be supplied at 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code-protect, both from an on state to an off state. for all other cases of icsp, the part may be programmed at the normal operating voltages. this means calibration values, unique user ids or user code can be reprogrammed or added. for complete details of serial programming, please refer to the ? pic16f87xa flash memory programming specification? (ds39589). 14.19 low-voltage (single-supply) icsp programming the lvp bit of the configuration word enables low- voltage icsp programming. this mode allows the microcontroller to be programmed via icsp using a v dd source in the operating voltage range. this only means that v pp does not have to be brought to v ihh but can instead be left at the normal operating voltage. in this mode, the rb3/pgm pin is dedicated to the pro- gramming function and ceases to be a general purpose i/o pin. during programming, v dd is applied to the mclr pin. to enter programming mode, v dd must be applied to the rb3/pgm provided the lvp bit is set. the lvp bit defaults to on (? 1 ?) from the factory. if low-voltage programming mode is not used, the lvp bit can be programmed to a ? 0 ? and rb3/pgm becomes a digital i/o pin. however, the lvp bit may only be pro- grammed when programming is entered with v ihh on mclr . the lvp bit can only be charged when using high voltage on mclr . it should be noted, that once the lvp bit is programmed to ? 0 ?, only the high-voltage programming mode is available and only high-voltage programming mode can be used to program the device. when using low-voltage icsp, the part must be supplied at 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code-protect bits from an on state to an off state. for all other cases of low-voltage icsp, the part may be programmed at the normal oper- ating voltage. this means calibration values, unique user ids or user code can be reprogrammed or added. note 1: the high-voltage programming mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr pin. 2: while in low-voltage icsp mode, the rb3 pin can no longer be used as a general purpose i/o pin. 3: when using low-voltage icsp program- ming (lvp) and the pull-ups on portb are enabled, bit 3 in the trisb register must be cleared to disable the pull-up on rb3 and ensure the proper operation of the device. 4: rb3 should not be allowed to float if lvp is enabled. an external pull-down device should be used to default the device to normal operating mode. if rb3 floats high, the pic16f87xa device will enter programming mode. 5: lvp mode is enabled by default on all devices shipped from microchip. it can be disabled by clearing the lvp bit in the config register. 6: disabling lvp will provide maximum compatibility to other pic16cxxx devices.
? 2003 microchip technology inc. ds39582b-page 159 pic16f87xa 15.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories: byte-oriented operations bit-oriented operations literal and control operations each pic16 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the formats for each of the categories is presented in figure 15-1, while the various opcode fields are summarized in table 15-1. table 15-2 lists the instructions recognized by the mpasm? assembler. a complete description of each instruction is also available in the picmicro ? mid-range mcu family reference manual (ds33023). for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the bit affected by the opera- tion, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an eight or eleven-bit constant or literal value one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 15.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a ? clrf portb ? instruction will read portb, clear all the data bits, then write the result back to portb. this example would have the unin- tended result that the condition that sets the rbif flag would be cleared. table 15-1: opcode field descriptions figure 15-1: general format for instructions note: to maintain upward compatibility with future pic16f87xa products, do not use the option and tris instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f87xa ds39582b-page 160 ? 2003 microchip technology inc. table 15-2: pic16f87xa instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023).
? 2003 microchip technology inc. ds39582b-page 161 pic16f87xa 15.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruc- tion is discarded and a nop is executed instead, making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b? in register ?f? is ? 0 ?, the next instruction is discarded and a nop is executed instead, making this a 2t cy instruction.
pic16f87xa ds39582b-page 162 ? 2003 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits, to and pd , are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2003 microchip technology inc. ds39582b-page 163 pic16f87xa decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruc- tion is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2 t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruc- tion is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2 t cy instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
pic16f87xa ds39582b-page 164 ? 2003 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. register f c register f c sleep syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd , is cleared. time-out status bit, to , is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2003 microchip technology inc. ds39582b-page 165 pic16f87xa swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16f87xa ds39582b-page 166 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page167 pic16f87xa 16.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? - picdem msc -microid ? -can - powersmart ? -analog 16.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 16.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
pic16f87xa ds39582b-page 168 ? 2003 microchip technology inc. 16.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 16.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of pre-compiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 16.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties, and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping, and math functions (trigonometric, exponen- tial and hyperbolic). the compiler provides symbolic information for high level source debugging with the mplab ide. 16.6 mplab asm30 assembler, linker, and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 16.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 16.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2003 microchip technology inc. ds39582b-page169 pic16f87xa 16.9 mplab ice 2000 high performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 16.10 mplab ice 4000 high performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory, and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 16.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab inte- grated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 16.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, and program picmicro devices without a pc connection. it can also set code protection in this mode. 16.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant.
pic16f87xa ds39582b-page 170 ? 2003 microchip technology inc. 16.14 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer, or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a pro- totype area extends the circuitry for additional applica- tion components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 16.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface, and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham. 16.16 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds, and sample pic18f452 and pic16f877 flash microcontrollers. 16.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 16.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14, and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 fam- ily of microcontrollers. picdem 4 is intended to show- case the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low power operation with the supercapacitor circuit, and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. included on the demo board are provisions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for program- ming via icsp and development with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a prototyping area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide. 16.19 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion.
? 2003 microchip technology inc. ds39582b-page171 pic16f87xa 16.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 16.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash micro- controller serves as the master. all three microcontrol- lers are programmed with firmware to provide lin bus communication. 16.22 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user's guide (on cd rom), pickit 1 tutorial software and code for vari- ous applications. also included are mplab ? ide (inte- grated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 16.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 16.24 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high power ir driver, delta sigma adc, and flow rate sensor check the microchip web page and the latest product line card for the complete list of demonstration and evaluation kits.
pic16f87xa ds39582b-page 172 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 173 pic16f87xa 17.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... .-55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr . and ra4) ......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v voltage on ra4 with respect to vss ............................................................................................. .....................0 to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb and porte (combined) (note 3) ....................................................200 ma maximum current sourced by porta, portb and porte (combined) (note 3) ...............................................200 ma maximum current sunk by portc and portd (combined) (note 3) .................................................................200 ma maximum current sourced by portc and portd (combined) (note 3) ............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr pin rather than pulling this pin directly to v ss . 3: portd and porte are not implemented on pic16f873a/876a devices. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16f87xa ds39582b-page 174 ? 2003 microchip technology inc. figure 17-1: pic16f87xa voltage-frequency graph (industrial, extended) figure 17-2: pic16lf87xa voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 20 mhz 5.0v 3.5v 3.0v 2.5v pic16f87xa frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 5.0v 3.5v 3.0v 2.5v f max = (6.0 mhz/v) (v ddappmin ? 2.0v) + 4 mhz note 1: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10 mhz. pic16lf87xa
? 2003 microchip technology inc. ds39582b-page 175 pic16f87xa 17.1 dc characteristics: pic16f873a/874a/876a/877a (industrial, extended) pic16lf873a/874a/876a/877a (industrial) pic16lf873a/874a/876a/877a (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f873a/874a/876a/877a (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic/ device min typ? max units conditions v dd supply voltage d001 16lf87xa 2.0 ? 5.5 v all configurations (dc to 10 mhz) d001 16f87xa 4.0 ? 5.5 v all configurations d001a v bor 5.5 v bor enabled, f max = 14 mhz (7) d002 v dr ram data retention voltage (1) ?1.5? v d003 v por v dd start voltage to ensure internal power-on reset signal ?v ss ?vsee section 14.5 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 14.5 ?power-on reset (por)? for details d005 v bor brown-out reset voltage 3.65 4.0 4.35 v boden bit in configuration word enabled legend: rows with standard voltage device data only are shaded for improved readability. ? data in ?typ? column is at 5v, 25c, unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16f87xa ds39582b-page 176 ? 2003 microchip technology inc. i dd supply current (2,5) d010 16lf87xa ? 0.6 2.0 ma xt, rc osc configurations, f osc = 4 mhz, v dd = 3.0v d010 16f87xa ? 1.6 4 ma xt, rc osc configurations, f osc = 4 mhz, v dd = 5.5v d010a 16lf87xa ? 20 35 a lp osc configuration, f osc = 32 khz, v dd = 3.0v, wdt disabled d013 16f87xa ? 7 15 ma hs osc configuration, f osc = 20 mhz, v dd = 5.5v d015 ? i bor brown-out reset current (6) ? 85 200 a bor enabled, v dd = 5.0v 17.1 dc characteristics: pic16f873a/874a/876a/877a (industrial, extended) pic16lf873a/874a/876a/877a (industrial) (continued) pic16lf873a/874a/876a/877a (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f873a/874a/876a/877a (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic/ device min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. ? data in ?typ? column is at 5v, 25c, unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
? 2003 microchip technology inc. ds39582b-page 177 pic16f87xa i pd power-down current (3,5) d020 16lf87xa ? 7.5 30 av dd = 3.0v, wdt enabled, -40 c to +85 c d020 16f87xa ? 10.5 42 60 a a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt enabled, -40 c to +125 c (extended) d021 16lf87xa ? 0.9 5 av dd = 3.0v, wdt disabled, 0 c to +70 c d021 16f87xa ? 1.5 16 20 a a v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c (extended) d021a 16lf87xa 0.9 5 av dd = 3.0v, wdt disabled, -40 c to +85 c d021a 16f87xa 1.5 19 a v dd = 4.0v, wdt disabled, -40 c to +85 c d023 ? i bor brown-out reset current (6) ? 85 200 a bor enabled, v dd = 5.0v 17.1 dc characteristics: pic16f873a/874a/876a/877a (industrial, extended) pic16lf873a/874a/876a/877a (industrial) (continued) pic16lf873a/874a/876a/877a (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f873a/874a/876a/877a (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic/ device min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. ? data in ?typ? column is at 5v, 25c, unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16f87xa ds39582b-page 178 ? 2003 microchip technology inc. 17.2 dc characteristics: pic16f873a/874a/876a/877a (industrial, extended) pic16lf873a/874a/876a/877a (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification ( section 17.1 ) param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss ?0.15 v dd v for entire v dd range d030a v ss ?0.8v v4.5v v dd 5.5v d031 with schmitt trigger buffer v ss ?0.2 v dd v d032 mclr , osc1 (in rc mode) v ss ?0.2 v dd v d033 osc1 (in xt and lp modes) v ss ?0.3v v (note 1) osc1 (in hs mode) v ss ?0.3 v dd v ports rc3 and rc4: ? d034 with schmitt trigger buffer v ss ?0.3 v dd v for entire v dd range d034a with smbus -0.5 ? 0.6 v for v dd = 4.5 to 5.5v v ih input high voltage i/o ports: ? d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a 0.25 v dd + 0.8v ?v dd v for entire v dd range d041 with schmitt trigger buffer 0.8 v dd ?v dd v for entire v dd range d042 mclr 0.8 v dd ?v dd v d042a osc1 (in xt and lp modes) 1.6v ? v dd v (note 1) osc1 (in hs mode) 0.7 v dd ?v dd v d043 osc1 (in rc mode) 0.9 v dd ?v dd v ports rc3 and rc4: d044 with schmitt trigger buffer 0.7 v dd ?v dd v for entire v dd range d044a with smbus 1.4 ? 5.5 v for v dd = 4.5 to 5.5v d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss , -40c to +85c i il input leakage current (2, 3) d060 i/o ports ? ? 1 av ss v pin v dd , pin at high-impedance d061 mclr , ra4/t0cki ? ? 5 av ss v pin v dd d063 osc1 ? ? 5 av ss v pin v dd , xt, hs and lp osc configuration * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f87xa be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage cu rrent may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 2003 microchip technology inc. ds39582b-page 179 pic16f87xa v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clko (rc osc config) ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c v oh output high voltage d090 i/o ports (3) v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clko (rc osc config) v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* v od open-drain high voltage ? ? 8.5 v ra4 pin capacitive loading specs on output pins d100 c osc 2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 d102 c io c b all i/o pins and osc2 (rc mode) scl, sda (i 2 c mode) ? ? ? ? 50 400 pf pf data eeprom memory d120 e d endurance 100k 1m ? e/w -40 c to +85 c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write, v min = min. operating voltage d122 t dew erase/write cycle time ? 4 8 ms program flash memory d130 e p endurance 10k 100k ? e/w -40 c to +85 c d131 v pr v dd for read v min ?5.5 vv min = min. operating voltage d132a v dd for erase/write v min ? 5.5 v using eecon to read/write, v min = min. operating voltage d133 t pew erase/write cycle time ? 4 8 ms 17.2 dc characteristics: pic16f873a/874a/876a/877a (industrial, extended) pic16lf873a/874a/876a/877a (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification ( section 17.1 ) param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f87xa be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage cu rrent may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16f87xa ds39582b-page 180 ? 2003 microchip technology inc. table 17-1: comparator specifications table 17-2: voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated) 4.0v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage* 0 - v dd ? 1.5 v d302 cmrr common mode rejection ratio* 55 - ? db 300 300a t resp response time* (1) ?150400 600 ns ns pic16f87xa pic16lf87xa 301 t mc 2 ov comparator mode change to output valid* ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2 while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated) 4.0v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated) spec no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? ? ? 1/2 1/2 lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) d312 vr ur unit resistor value (r)* ? 2k ? ? 310 t set settling time* (1) ? ? 10 s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from ? 0000 ? to ? 1111 ?.
? 2003 microchip technology inc. ds39582b-page 181 pic16f87xa 17.3 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 17-3: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports, 15 pf for osc2 output note: portd and porte are not implemented on pic16f873a/876a devices. load condition 1 load condition 2
pic16f87xa ds39582b-page 182 ? 2003 microchip technology inc. figure 17-4: external clock timing osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 17-3: external clock timing requirements param no. symbol characteristic min typ? max units conditions f osc external clki frequency (note 1) dc ? 1 mhz xt and rc osc mode dc ? 20 mhz hs osc mode dc ? 32 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 4 5 ? ? 20 200 mhz khz hs osc mode lp osc mode 1t osc external clki period (note 1) 1000 ? ? ns xt and rc osc mode 50 ? ? ns hs osc mode 5?? slp osc mode oscillator period (note 1) 250 ? ? ns rc osc mode 250 ? 1 s xt osc mode 100 ? 250 ns hs osc mode 50 ? 250 ns hs osc mode 31.25 ? ? slp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3t os l, t os h external clock in (osc1) high or low time 100 ? ? ns xt oscillator 2.5 ? ? s lp oscillator 15 ? ? ns hs oscillator 4t os r, t os f external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ? ? 15 ns hs oscillator ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
? 2003 microchip technology inc. ds39582b-page 183 pic16f87xa figure 17-5: clko and i/o timing table 17-4: clko and i/o timing requirements note: refer to figure 17-3 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ? max units conditions 10* t os h2 ck losc1 to clko ? 75 200 ns (note 1) 11* t os h2 ck hosc1 to clko ? 75 200 ns (note 1) 12* t ck r clko rise time ? 35 100 ns (note 1) 13* t ck f clko fall time ? 35 100 ns (note 1) 14* t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15* t io v2 ck h port in valid before clko t osc + 200 ? ? ns (note 1) 16* t ck h2 io i port in hold after clko 0??ns (note 1) 17* t os h2 io vosc1 (q1 cycle) to port out valid ? 100 255 ns 18* t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) standard ( f ) 100 ? ? ns extended ( lf ) 200 ? ? ns 19* t io v2 os h port input valid to osc1 (i/o in setup time) 0 ? ? ns 20* t io r port output rise time standard ( f ) ? 10 40 ns extended ( lf ) ? ? 145 ns 21* t io f port output fall time standard ( f ) ? 10 40 ns extended ( lf ) ? ? 145 ns 22??* t inp int pin high or low time t cy ??ns 23??* t rbp rb7:rb4 change int high or low time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clko output is 4 x t osc .
pic16f87xa ds39582b-page 184 ? 2003 microchip technology inc. figure 17-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 17-7: brown-out reset timing table 17-5: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 17-3 for load conditions. v dd v bor 35 param no. symbol characteristic min typ? max units conditions 30 t mc lmclr pulse width (low) 2 ? ? sv dd = 5v, -40c to +85c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.1 s 35 t bor brown-out reset pulse width 100 ? ? sv dd v bor (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested.
? 2003 microchip technology inc. ds39582b-page 185 pic16f87xa figure 17-8: timer0 and timer1 external clock timings table 17-6: timer0 and timer1 external clock requirements param no. symbol characteristic min typ? max units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 42* t t 0p t0cki period no prescaler t cy + 40 ? ? ns with prescaler greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4,..., 256) 45* t t 1h t1cki high time synchronous, prescaler = 1 0.5 t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2, 4, 8 standard( f )15??ns extended( lf )25 ??ns asynchronous standard( f )30??ns extended( lf )50 ??ns 46* t t 1l t1cki low time synchronous, prescaler = 1 0.5 t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2, 4, 8 standard( f )15??ns extended( lf )25 ??ns asynchronous standard( f )30??ns extended( lf )50 ??ns 47* t t 1p t1cki input period synchronous standard( f ) greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) extended( lf ) greater of: 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard( f )60??ns extended( lf ) 100 ? ? ns f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200 khz 48 tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note: refer to figure 17-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16f87xa ds39582b-page 186 ? 2003 microchip technology inc. figure 17-9: capture/compare/pwm timings (ccp1 and ccp2) table 17-7: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 17-3 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2 param no. symbol characteristic min typ? max units conditions 50* t cc l ccp1 and ccp2 input low time no prescaler 0.5 t cy + 20 ? ? ns with prescaler standard( f )10??ns extended( lf )20??ns 51* t cc h ccp1 and ccp2 input high time no prescaler 0.5 t cy + 20 ? ? ns with prescaler standard( f )10??ns extended( lf )20??ns 52* t cc p ccp1 and ccp2 input period 3 t cy + 40 n ? ? ns n = prescale value (1, 4 or 16) 53* t cc r ccp1 and ccp2 output rise time standard( f ) ? 10 25 ns extended( lf ) ? 25 50 ns 54* t cc f ccp1 and ccp2 output fall time standard( f ) ? 10 25 ns extended( lf ) ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested.
? 2003 microchip technology inc. ds39582b-page 187 pic16f87xa figure 17-10: parallel slave port timing (pic16f874a/877a only) table 17-8: parallel slave port requirements (pic16f874a/877a only) note: refer to figure 17-3 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param no. symbol characteristic min typ? max units conditions 62 t dt v2 wr h data in valid before wr or cs (setup time) 20 ? ? ns 63* t wr h2 dt iwr or cs to data?in invalid (hold time) standard( f )20??ns extended( lf )35??ns 64 t rd l2 dt vrd and cs to data?out valid ? ? 80 ns 65 t rd h2 dt ird or cs to data?out invalid 10 ? 30 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested.
pic16f87xa ds39582b-page 188 ? 2003 microchip technology inc. figure 17-11: spi master mode timing (cke = 0 , smp = 0 ) figure 17-12: spi master mode timing (cke = 1 , smp = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 17-3 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 17-3 for load conditions.
? 2003 microchip technology inc. ds39582b-page 189 pic16f87xa figure 17-13: spi slave mode timing (cke = 0 ) figure 17-14: spi slave mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 17-3 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 17-3 for load conditions.
pic16f87xa ds39582b-page 190 ? 2003 microchip technology inc. table 17-9: spi mode requirements figure 17-15: i 2 c bus start/stop bits timing param no. symbol characteristic min typ? max units conditions 70* t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ??ns 71* t sc h sck input high time (slave mode) t cy + 20 ? ? ns 72* t sc l sck input low time (slave mode) t cy + 20 ? ? ns 73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ? ns 74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ? ns 75* t do r sdo data output rise time standard( f ) extended( lf ) ? ? 10 25 25 50 ns ns 76* t do f sdo data output fall time ? 10 25 ns 77* t ss h2 do zss to sdo output high-impedance 10 ? 50 ns 78* t sc r sck output rise time (master mode) standard( f ) extended( lf ) ? ? 10 25 25 50 ns ns 79* t sc f sck output fall time (master mode) ? 10 25 ns 80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge standard( f ) extended( lf ) ? ? ? ? 50 145 ns 81* t do v2 sc h, t do v2 sc l sdo data output setup to sck edge t cy ??ns 82* t ss l2 do v sdo data output valid after ss edge ? ? 50 ns 83* t sc h2 ss h, t sc l2 ss h ss after sck edge 1.5 t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 17-3 for load conditions. 91 93 scl sda start condition stop condition 90 92
? 2003 microchip technology inc. ds39582b-page 191 pic16f87xa table 17-10: i 2 c bus start/stop bits requirements figure 17-16: i 2 c bus data timing param no. symbol characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? 91 t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? 92 t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? note: refer to figure 17-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16f87xa ds39582b-page 192 ? 2003 microchip technology inc. table 17-11: i 2 c bus data requirements param no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s 400 khz mode 0.6 ? s ssp module 0.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s 400 khz mode 1.3 ? s ssp module 0.5 t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns cb is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provi de this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement that, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max . + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
? 2003 microchip technology inc. ds39582b-page 193 pic16f87xa figure 17-17: usart synchronous transmission (master/slave) timing table 17-12: usart synchronous transmission requirements figure 17-18: usart synchronous receive (master/slave) timing table 17-13: usart synchronous receive requirements note: refer to figure 17-3 for load conditions. 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 param no. symbol characteristic min typ? max units conditions 120 t ck h2 dt v sync xmit (master & slave) clock high to data out valid standard( f )??80ns extended( lf ) ? ? 100 ns 121 t ckrf clock out rise time and fall time (master mode) standard( f )??45ns extended( lf )??50ns 122 t dtrf data out rise time and fall time standard( f )??45ns extended( lf )??50ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 17-3 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin param no. symbol characteristic min typ? max units conditions 125 t dt v2 ck l sync rcv (master & slave) data setup before ck (dt setup time) 15 ? ? ns 126 t ck l2 dtl data hold after ck (dt hold time) 15 ? ? ns ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16f87xa ds39582b-page 194 ? 2003 microchip technology inc. table 17-14: a/d converter characteristics:pic16f873a/874a/876a/877a (industrial) pic16lf873a/874a/876a/877a (industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 10-bits bit v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error ? ? < 2 lsb v ref = v dd = 5.12v, v ss v ain v ref a07 e gn gain error ? ? < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 ? monotonicity ? guaranteed (3) ??v ss v ain v ref a20 v ref reference voltage (v ref + ? v ref -) 2.0 ? v dd + 0.3 v a21 v ref + reference voltage high av dd ? 2.5v av dd + 0.3v v a22 v ref - reference voltage low av ss ? 0.3v v ref + ? 2.0v v a25 v ain analog input voltage v ss ? 0.3v ? v ref + 0.3v v a30 z ain recommended impedance of analog voltage source ??2.5k ? (note 4) a40 i ad a/d conversion current (v dd ) pic16f87xa ? 220 ? a average current consumption when a/d is on (note 1) pic16lf87xa ? 90 ? a a50 i ref v ref input current (note 2) ? ? ? ? 5 150 a a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 11.1 ?a/d acquisition requirements? . during a/d conversion cycle * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. t he power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never dec reases with an increase in the input voltage and has no missing codes. 4: maximum allowed impedance for analog voltage source is 10 k ?. this requires higher acquisition time.
? 2003 microchip technology inc. ds39582b-page 195 pic16f87xa figure 17-19: a/d conversion timing table 17-15: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 987 210 note: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy . . . . . . param no. symbol characteristic min typ? max units conditions 130 t ad a/d clock period pic16f87xa 1.6 ? ? st osc based, v ref 3.0v pic16lf87xa 3.0 ? ? st osc based, v ref 2.0v pic16f87xa 2.0 4.0 6.0 s a/d rc mode pic16lf87xa 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) ?12t ad 132 t acq acquisition time (note 2) 10* 40 ? ? ? s s the minimum time is the amplifier settling time. this may be used if the ?new? input volt- age has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. this specification ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see section 11.1 ?a/d acquisition requirements? for minimum conditions.
pic16f87xa ds39582b-page 196 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39582b-page 197 pic16f87xa 18.0 dc and ac characteristics graphs and tables ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean ? 3 ) respectively, where is a standard deviation, over the whole temperature range. figure 18-1: typical i dd vs. f osc over v dd (hs mode) figure 18-2: maximum i dd vs. f osc over v dd (hs mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 1 2 3 4 5 6 7 4 6 8 10 12 14 16 18 20 f osc (mhz) i dd (ma) 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 1 2 3 4 5 6 7 8 4 6 8 10 12 14 16 18 20 f osc (mhz) i dd (ma) 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic16f87xa ds39582b-page 198 ? 2003 microchip technology inc. figure 18-3: typical i dd vs. f osc over v dd (xt mode) figure 18-4: maximum i dd vs. f osc over v dd (xt mode) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 500 1000 1500 2000 2500 3000 3500 4000 f osc (mhz) i dd (ma) 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 0 500 1000 1500 2000 2500 3000 3500 4000 f osc (mhz) i dd (ma) 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39582b-page 199 pic16f87xa figure 18-5: typical i dd vs. f osc over v dd (lp mode) figure 18-6: maximum i dd vs. f osc over v dd (lp mode) 0 10 20 30 40 50 60 70 20 30 40 50 60 70 80 90 100 f osc (khz) i dd (ua) 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 20 40 60 80 100 120 20 30 40 50 60 70 80 90 100 f osc (khz) i dd (ua) 2.0v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic16f87xa ds39582b-page 200 ? 2003 microchip technology inc. figure 18-7: average f osc vs. v dd for various values of r (rc mode, c = 20 pf, +25 c) figure 18-8: average f osc vs. v dd for various values of r (rc mode, c = 100 pf, +25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 100 kohm 10 kohm 5.1 kohm operation above 4 mhz is not recommended 0.0 0.5 1.0 1.5 2.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 100 kohm 10 kohm 5.1 kohm 3.3 kohm
? 2003 microchip technology inc. ds39582b-page 201 pic16f87xa figure 18-9: average f osc vs. v dd for various values of r (rc mode, c = 300 pf, +25 c) figure 18-10: i pd vs. v dd , -40 c to +125 c (sleep mode, all peripherals disabled) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 100 kohm 10 kohm 5.1 kohm 3.3 kohm 0.001 0.01 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typ (25c) max (85c) max (125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic16f87xa ds39582b-page 202 ? 2003 microchip technology inc. figure 18-11: typical and maximum ? i tmr1 vs. v dd over temperature (-10 c to +70 c, timer1 with oscillator, xtal = 32 khz, c1 and c2 = 47 pf) figure 18-12: typical and maximum ? i wdt vs. v dd over temperature (wdt enabled) 0 2 4 6 8 10 12 14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typ (25c) max (70c) typical: statistical mean @ 25c maximum: mean + 3 (-10c to +70c) minimum: mean ? 3 (-10c to +70c) i pd ( a) max (+70c) typ (+25c) 0.1 1 10 100 2.02.53.03.54.04.55.05.5 v dd (v) i pd (ua) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) max (+125c) max (+85c) typ (+25c)
? 2003 microchip technology inc. ds39582b-page 203 pic16f87xa figure 18-13: ? i bor vs. v dd over temperature figure 18-14: typical, minimum and maximum wdt period vs. v dd (-40 c to +125 c) 10 100 1,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) device in reset device in sleep indeterminant state max (125c) typ (25c) max (125c) typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) note: device current in reset depends on oscillator mode, frequency and circuit. 0 5 10 15 20 25 30 35 40 45 50 2.02.53.03.54.04.55.05.5 v dd (v) wdt period (ms) max (125c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic16f87xa ds39582b-page 204 ? 2003 microchip technology inc. figure 18-15: average wdt period vs. v dd over temperature (-40 c to +125 c) figure 18-16: typical, minimum and maximum v oh vs. i oh (v dd = 5v, -40 c to +125 c) 0 5 10 15 20 25 30 35 40 45 50 2.02.53.03.54.04.55.05.5 v dd (v) wdt period (ms) 125c 85c 25c -40c typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 i oh (-ma) v oh (v) max typ (25c) min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39582b-page 205 pic16f87xa figure 18-17: typical, minimum and maximum v oh vs. i oh (v dd = 3v, -40 c to +125 c) figure 18-18: typical, minimum and maximum v ol vs. i ol (v dd = 5v, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 i oh (-ma) v oh (v) max typ (25c) min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic16f87xa ds39582b-page 206 ? 2003 microchip technology inc. figure 18-19: typical, minimum and maximum v ol vs. i ol (v dd = 3v, -40 c to +125 c) figure 18-20: minimum and maximum v in vs. v dd (ttl input, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 2.02.53.03.54.04.55.05.5 v dd (v) v in (v) v th max (-40c) v th min (125c) v th typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39582b-page 207 pic16f87xa figure 18-21: minimum and maximum v in vs. v dd (st input, -40 c to +125 c) figure 18-22: minimum and maximum v in vs. v dd (i 2 c input, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max (125c) v ih min (-40c) v il max (-40c) v il min (125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max v ih min v il max v il min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) v il max
pic16f87xa ds39582b-page 208 ? 2003 microchip technology inc. figure 18-23: a/d nonlinearity vs. v refh (v dd = v refh , -40 c to +125 c) figure 18-24: a/d nonlinearity vs. v refh (v dd = 5v, -40 c to +125 c) 0 0.5 1 1.5 2 2.5 3 3.5 4 22.533.544.555.5 v dd and v refh (v) differential or integral nonlinearity (lsb) -40c 25c 85c 125c -40c +25c +85c +125c 0 0.5 1 1.5 2 2.5 3 22.533.544.555.5 v refh (v) differential or integral nonlinearilty (lsb) max (-40c to 125c) typ (25c) typ (+25c) max (-40c to +125c)
? 2003 microchip technology inc. ds39582b-page 209 pic16f87xa 19.0 packaging information 19.1 package marking information 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn example pic16f877a/p 0310017 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic16f877a /pt 0310017 44-lead plcc xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic16f877a -20/l 0310017 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic16f87xa ds39582b-page 210 ? 2003 microchip technology inc. package marking information (cont?d) xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn example 28-lead pdip (skinny dip) xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic16f876a/sp 0310017 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic16f876a/so 0310017 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic16f876a/ ss 0310017 example 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn pic16f877a -i/ml 0310017 16f873a -i/ml 0310017
? 2003 microchip technology inc. ds39582b-page 211 pic16f87xa 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic
pic16f87xa ds39582b-page 212 ? 2003 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 ch x 45 significant characteristic
? 2003 microchip technology inc. ds39582b-page 213 pic16f87xa 44-lead plastic leaded chip carrier (l) ? square (plcc) ch2 x 45 ch1 x 45 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 11 11 n1 pins per side 16.00 15.75 14.99 .630 .620 .590 d2 footprint length 16.00 15.75 14.99 .630 .620 .590 e2 footprint width 16.66 16.59 16.51 .656 .653 .650 d1 molded package length 16.66 16.59 16.51 .656 .653 .650 e1 molded package width 17.65 17.53 17.40 .695 .690 .685 d overall length 17.65 17.53 17.40 .695 .690 .685 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p a3 a 35 b1 b d2 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 lower lead width * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-048 significant characteristic
pic16f87xa ds39582b-page 214 ? 2003 microchip technology inc. 44-lead plastic quad flat no lead package (ml) 8x8 mm body (qfn) lead width *controlling parameter drawing no. c04-103 notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per side. b .012 .013 .013 0.30 0.33 0.35 pitch number of pins overall width standoff overall length overall height max units dimension limits a1 d e n p a .315 bsc .000 inches .026 bsc min 44 nom max .002 0 8.00 bsc millimeters* .039 min 44 0.65 bsc nom 0.05 1.00 .010 ref base thickness a3 0.25 ref jedec equivalent: m0-220 0.90 .035 .001 0.02 .315 bsc 8.00 bsc lead length l .014 .016 .018 0.35 0.40 0.45 e2 d2 exposed pad width exposed pad length .262 .268 .274 6.65 6.80 6.95 .262 .268 .274 6.65 6.80 6.95 d2 d a1 a3 a top view n 1 l e2 bottom view b e 2 pad metal exposed p pin 1 index on exposed pad top marking index on optional pin 1 .031 0.80
? 2003 microchip technology inc. ds39582b-page 215 pic16f87xa 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic
pic16f87xa ds39582b-page 216 ? 2003 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
? 2003 microchip technology inc. ds39582b-page 217 pic16f87xa 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l c a2 a1 a significant characteristic
pic16f87xa ds39582b-page 218 ? 2003 microchip technology inc. 28-lead plastic quad flat no lead package (ml) 6x6 mm body, punch singulated (qfn) lead width *controlling parameter drawing no. c04-114 notes: mold draft angle top dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per side. b .009 12 .011 .014 0.23 12 0.28 0.35 pitch number of pins overall width standoff molded package length overall length molded package width molded package thickness overall height max units dimension limits a2 a1 e1 d d1 e n p a .026 .236 bsc .000 .226 bsc inches .026 bsc min 28 nom max 0.65 .031 .002 0.00 6.00 bsc 5.75 bsc millimeters* .039 min 28 0.65 bsc nom 0.80 0.05 1.00 .008 ref base thickness a3 0.20 ref jedec equivalent: mmo-220 0.85 .033 .0004 0.01 .236 bsc .226 bsc 6.00 bsc 5.75 bsc lead length tie bar width l .020 .024 .030 0.50 0.60 0.75 r .005 .007 .010 0.13 0.17 0.23 tie bar length q .012 .016 .026 0.30 0.40 0.65 chamfer ch .009 .017 .024 0.24 0.42 0.60 e2 d2 exposed pad width exposed pad length .140 .146 .152 3.55 3.70 3.85 .140 .146 .152 3.55 3.70 3.85 d e e1 n 1 2 d1 a a2 exposed metal pads bottom view top view q l r p a1 a3 ch x 45 b d2 e2
? 2003 microchip technology inc. ds39582b-page 219 pic16f87xa appendix a: revision history revision a (november 2001) original data sheet for pic16f87xa devices. the devices presented are enhanced versions of the pic16f87x microcontrollers discussed in the ? pic16f87x data sheet? (ds30292). revision b (october 2003) this revision includes the dc and ac characteristics graphs and tables. the electrical specifications in section 17.0 ?electrical characteristics? have been updated and there have been minor corrections to the data sheet text. appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. table b-1: differences between devices in the pic16f87xa family pic16f873a pic16f874a pic16f876a pic16f877a flash program memory (14-bit words) 4k 4k 8k 8k data memory (bytes) 192 192 368 368 eeprom data memory (bytes) 128 128 256 256 interrupts 14 15 14 15 i/o ports ports a, b, c ports a, b, c, d, e ports a, b, c ports a, b, c, d, e serial communications mssp, usart mssp, usart mssp, usart mssp, usart parallel slave port no yes no yes 10-bit analog-to-digital module 5 input channels 8 input channels 5 input channels 8 input channels packages 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin plcc 44-pin tqfp 44-pin qfn 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 44-pin plcc 44-pin tqfp 44-pin qfn
pic16f87xa ds39582b-page 220 ? 2003 microchip technology inc. appendix c: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table c-1. table c-1: conversion considerations characteristic pic16c7x pic16f87x pic16f87xa pins 28/40 28/40 28/40 timers 3 3 3 interrupts 11 or 12 13 or 14 14 or 15 communication psp, usart, ssp (spi, i 2 c slave) psp, usart, ssp (spi, i 2 c master/slave) psp, usart, ssp (spi, i 2 c master/slave) frequency 20 mhz 20 mhz 20 mhz voltage 2.5v-5.5v 2.2v-5.5v 2.0v-5.5v a/d 8-bit, 4 conversion clock selects 10-bit, 4 conversion clock selects 10-bit, 7 conversion clock selects ccp 2 2 2 comparator ? ? 2 comparator voltage reference ??yes program memory 4k, 8k eprom 4k, 8k flash (erase/write on single-word) 4k, 8k flash (erase/write on four-word blocks) ram 192, 368 bytes 192, 368 bytes 192, 368 bytes eeprom data none 128, 256 bytes 128, 256 bytes code protection on/off segmented, starting at end of program memory on/off program memory write protection ? on/off segmented, starting at beginning of program memory other ? in-circuit debugger, low-voltage programming in-circuit debugger, low-voltage programming
? 2003 microchip technology inc. ds39582b-page 221 pic16f87xa index a a/d ................................................................................... 127 acquisition requirements ........................................ 130 adcon0 register .................................................... 127 adcon1 register .................................................... 127 adif bit .................................................................... 129 adresh register .................................................... 127 adresl register .................................................... 127 analog port pins .................................................. 49 , 51 associated registers and bits ................................. 133 calculating acquisition time .................................... 130 configuring analog port pins ................................... 131 configuring the interrupt .......................................... 129 configuring the module ............................................ 129 conversion clock ..................................................... 131 conversions ............................................................. 132 converter characteristics ........................................ 194 effects of a reset ..................................................... 133 go/done bit ........................................................... 129 internal sampling switch (rss) impedance ............. 130 operation during sleep ........................................... 133 result registers ....................................................... 132 source impedance ................................................... 130 a/d conversion requirements ......................................... 195 absolute maximum ratings ............................................. 173 ackstat ......................................................................... 101 adcon0 register .............................................................. 19 adcon1 register .............................................................. 20 addressable universal synchronous asynchronous receiver transmitter. see usart. adresh register .............................................................. 19 adresl register .............................................................. 20 analog-to-digital converter. see a/d. application notes an552 (implementing wake-up on key stroke) ................................................... 44 an556 (implementing a table read) ........................ 30 assembler mpasm assembler .................................................. 167 asynchronous reception associated registers ....................................... 118 , 120 asynchronous transmission associated registers ............................................... 116 b banking, data memory ................................................. 16 , 22 baud rate generator ......................................................... 97 associated registers ............................................... 113 bclif ................................................................................. 28 bf ..................................................................................... 101 block diagrams a/d ........................................................................... 129 analog input model .......................................... 130 , 139 baud rate generator ................................................. 97 capture mode operation ........................................... 65 comparator i/o operating modes ............................ 136 comparator output .................................................. 138 comparator voltage reference ............................... 142 compare mode operation ......................................... 66 crystal/ceramic resonator operation (hs, xt or lp osc configuration) .................... 145 external clock input operation (hs, xt or lp osc configuration) .................... 145 interrupt logic .......................................................... 153 mssp (i 2 c mode) ...................................................... 80 mssp (spi mode) ..................................................... 71 on-chip reset circuit .............................................. 147 pic16f873a/pic16f876a architecture ...................... 6 pic16f874a/pic16f877a architecture ...................... 7 portc peripheral output override (rc2:0, rc7:5) pins .................................. 46 peripheral output override (rc4:3) pins .......... 46 portd (in i/o port mode) ......................................... 48 portd and porte (parallel slave port) ................. 51 porte (in i/o port mode) ......................................... 49 ra3:ra0 pins ............................................................ 41 ra4/t0cki pin .......................................................... 42 ra5 pin ..................................................................... 42 rb3:rb0 pins ............................................................ 44 rb7:rb4 pins ............................................................ 44 rc oscillator mode .................................................. 146 recommended mclr circuit .................................. 148 simplified pwm mode ............................................... 67 timer0/wdt prescaler .............................................. 53 timer1 ....................................................................... 58 timer2 ....................................................................... 61 usart receive ................................................117 , 119 usart transmit ...................................................... 115 watchdog timer ...................................................... 155 bor. see brown-out reset. brg. see baud rate generator. brgh bit ......................................................................... 113 brown-out reset (bor) .................... 143 , 147 , 148 , 149 , 150 bor status (bor bit) ............................................... 29 bus collision during a repeated start condition ............ 108 bus collision during a start condition ............................. 106 bus collision during a stop condition ............................. 109 bus collision interrupt flag bit, bclif ............................... 28 c c compilers mplab c17 ............................................................. 168 mplab c18 ............................................................. 168 mplab c30 ............................................................. 168 capture/compare/pwm (ccp) ......................................... 63 associated registers capture, compare and timer1 .......................... 68 pwm and timer2 ............................................... 69 capture mode ............................................................ 65 ccp1if .............................................................. 65 prescaler ........................................................... 65 ccp timer resources ............................................... 63 compare special event trigger output of ccp1 .............. 66 special event trigger output of ccp2 .............. 66 compare mode .......................................................... 66 software interrupt mode .................................... 66 special event trigger ........................................ 66 interaction of two ccp modules (table) .................... 63 pwm mode ................................................................ 67 duty cycle ......................................................... 67 example frequencies/resolutions (table) ......... 68 pwm period ...................................................... 67 special event trigger and a/d conversions ............. 66
pic16f87xa ds39582b-page 222 ? 2003 microchip technology inc. capture/compare/pwm requirements (ccp1 and ccp2) .................................................... 186 ccp. see capture/compare/pwm. ccp1con register ........................................................... 19 ccp2con register ........................................................... 19 ccpr1h register ........................................................ 19 , 63 ccpr1l register ......................................................... 19 , 63 ccpr2h register ........................................................ 19 , 63 ccpr2l register ......................................................... 19 , 63 ccpxm0 bit ........................................................................ 64 ccpxm1 bit ........................................................................ 64 ccpxm2 bit ........................................................................ 64 ccpxm3 bit ........................................................................ 64 ccpxx bit .......................................................................... 64 ccpxy bit .......................................................................... 64 clko and i/o timing requirements ............................... 183 cmcon register ............................................................... 20 code examples call of a subroutine in page 1 from page 0 ............... 30 indirect addressing .................................................... 31 initializing porta ...................................................... 41 loading the sspbuf (sspsr) register ................... 74 reading data eeprom ............................................. 35 reading flash program memory ............................... 36 saving status, w and pclath registers in ram ............................................................ 154 writing to data eeprom ........................................... 35 writing to flash program memory ............................. 38 code protection ....................................................... 143 , 157 comparator module ......................................................... 135 analog input connection considerations ................................................. 139 associated registers ............................................... 140 configuration ............................................................ 136 effects of a reset ..................................................... 139 interrupts .................................................................. 138 operation ................................................................. 137 operation during sleep ............................................ 139 outputs ..................................................................... 137 reference ................................................................. 137 response time ........................................................ 137 comparator specifications ............................................... 180 comparator voltage reference ....................................... 141 associated registers ............................................... 142 computed goto ............................................................... 30 configuration bits ............................................................. 143 configuration word .......................................................... 144 conversion considerations .............................................. 220 cvrcon register ............................................................. 20 d data eeprom and flash program memory eeadr register ........................................................ 33 eeadrh register ...................................................... 33 eecon1 register ...................................................... 33 eecon2 register ...................................................... 33 eedata register ...................................................... 33 eedath register ...................................................... 33 data eeprom memory associated registers ................................................. 39 eeadr register ........................................................ 33 eeadrh register ..................................................... 33 eecon1 register ...................................................... 33 eecon2 register ...................................................... 33 operation during code-protect ................................. 39 protection against spurious writes ........................... 39 reading ..................................................................... 35 write complete flag bit (eeif) ................................. 33 writing ........................................................................ 35 data memory ..................................................................... 16 bank select (rp1:rp0 bits) .................................16 , 22 general purpose registers ....................................... 16 register file map ..................................................17 , 18 special function registers ........................................ 19 dc and ac characteristics graphs and tables .............. 197 dc characteristics ....................................................175 ? 179 demonstration boards picdem 1 ................................................................ 170 picdem 17 .............................................................. 170 picdem 18r pic18c601/801 ................................. 171 picdem 2 plus ........................................................ 170 picdem 3 pic16c92x ............................................ 170 picdem 4 ................................................................ 170 picdem lin pic16c43x ........................................ 171 picdem usb pic16c7x5 ...................................... 171 picdem.net internet/ethernet ................................. 170 development support ...................................................... 167 device differences ........................................................... 219 device overview .................................................................. 5 direct addressing ............................................................... 31 e eeadr register ...........................................................21 , 33 eeadrh register .........................................................21 , 33 eecon1 register .........................................................21 , 33 eecon2 register .........................................................21 , 33 eedata register .............................................................. 21 eedath register .............................................................. 21 electrical characteristics .................................................. 173 errata ................................................................................... 4 evaluation and programming tools ................................. 171 external clock timing requirements ............................... 182 external interrupt input (rb0/int). see interrupt sources. external reference signal ............................................... 137 f firmware instructions ....................................................... 159 flash program memory associated registers ................................................. 39 eecon1 register ...................................................... 33 eecon2 register ...................................................... 33 reading ..................................................................... 36 writing ........................................................................ 37 fsr register ..........................................................19 , 20 , 31 g general call address support ........................................... 94
? 2003 microchip technology inc. ds39582b-page 223 pic16f87xa i i/o ports ............................................................................. 41 i2c bus data requirements ............................................ 192 i 2 c bus start/stop bits requirements ............................. 191 i 2 c mode registers .................................................................... 80 i 2 c mode ............................................................................ 80 ack pulse ............................................................ 84 , 85 acknowledge sequence timing ............................... 104 baud rate generator ................................................. 97 bus collision repeated start condition ................................. 108 start condition ................................................. 106 stop condition ................................................. 109 clock arbitration ......................................................... 98 effect of a reset ...................................................... 105 general call address support ................................... 94 master mode .............................................................. 95 operation ........................................................... 96 repeated start timing ..................................... 100 master mode reception ........................................... 101 master mode start condition ..................................... 99 master mode transmission ...................................... 101 multi-master communication, bus collision and arbitration .................................................. 105 multi-master mode ................................................... 105 read/write bit information (r/w bit) ................... 84 , 85 serial clock (rc3/sck/scl) ..................................... 85 slave mode ................................................................ 84 addressing ......................................................... 84 reception ........................................................... 85 transmission ...................................................... 85 sleep operation ....................................................... 105 stop condition timing .............................................. 104 id locations ............................................................. 143 , 157 in-circuit debugger .................................................. 143 , 157 resources ................................................................ 157 in-circuit serial programming (icsp) ...................... 143 , 158 indf register .........................................................19 , 20 , 31 indirect addressing ............................................................ 31 fsr register ............................................................. 16 instruction format ............................................................ 159 instruction set .................................................................. 159 addlw .................................................................... 161 addwf .................................................................... 161 andlw .................................................................... 161 andwf .................................................................... 161 bcf .......................................................................... 161 bsf .......................................................................... 161 btfsc ..................................................................... 161 btfss ..................................................................... 161 call ........................................................................ 162 clrf ........................................................................ 162 clrw ...................................................................... 162 clrwdt .................................................................. 162 comf ...................................................................... 162 decf ....................................................................... 162 decfsz ................................................................... 163 goto ...................................................................... 163 incf ......................................................................... 163 incfsz .................................................................... 163 iorlw ..................................................................... 163 iorwf ..................................................................... 163 return .................................................................. 164 rlf .......................................................................... 164 rrf ......................................................................... 164 sleep ..................................................................... 164 sublw .................................................................... 164 subwf .................................................................... 164 swapf .................................................................... 165 xorlw ................................................................... 165 xorwf ................................................................... 165 summary table ....................................................... 160 int interrupt (rb0/int). see interrupt sources. intcon register ............................................................... 24 gie bit ....................................................................... 24 inte bit ..................................................................... 24 intf bit ..................................................................... 24 peie bit ..................................................................... 24 rbie bit ..................................................................... 24 rbif bit ................................................................24 , 44 tmr0ie bit ................................................................ 24 tmr0if bit ................................................................. 24 inter-integrated circuit. see i 2 c. internal reference signal ................................................ 137 internal sampling switch (rss) impedance ..................... 130 interrupt sources ......................................................143 , 153 interrupt-on-change (rb7:rb4) ................................ 44 rb0/int pin, external .....................................9 , 11 , 154 tmr0 overflow ........................................................ 154 usart receive/transmit complete ....................... 111 interrupts bus collision interrupt ................................................ 28 synchronous serial port interrupt .............................. 26 interrupts, context saving during .................................... 154 interrupts, enable bits global interrupt enable (gie bit) ........................24 , 153 interrupt-on-change (rb7:rb4) enable (rbie bit) .......................................24 , 154 peripheral interrupt enable (peie bit) ....................... 24 rb0/int enable (inte bit) ........................................ 24 tmr0 overflow enable (tmr0ie bit) ........................ 24 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) .............................................. 24 , 44 , 154 rb0/int flag (intf bit) ............................................ 24 tmr0 overflow flag (tmr0if bit) .....................24 , 154 l loading of pc .................................................................... 30 low-voltage icsp programming ..................................... 158 low-voltage in-circuit serial programming ..................... 143 m master clear (mclr ) ........................................................... 8 mclr reset, normal operation ............... 147 , 149 , 150 mclr reset, sleep .................................. 147 , 149 , 150 master synchronous serial port (mssp). see mssp. mclr ............................................................................... 148 mclr /v pp ......................................................................... 10 memory organization ........................................................ 15 data eeprom memory ............................................. 33 data memory ............................................................. 16 flash program memory ............................................. 33 program memory ....................................................... 15 mplab asm30 assembler, linker, librarian .................. 168 mplab icd 2 in-circuit debugger .................................. 169 mplab ice 2000 high-performance universal in-circuit emulator ................................................... 169
pic16f87xa ds39582b-page 224 ? 2003 microchip technology inc. mplab ice 4000 high-performance universal in-circuit emulator ................................................... 169 mplab integrated development environment software .............................................. 167 mplink object linker/mplib object librarian ............... 168 mssp ................................................................................. 71 i 2 c mode. see i 2 c. spi mode ................................................................... 71 spi mode. see spi. mssp module clock stretching ......................................................... 90 clock synchronization and the ckp bit ..................... 91 control registers (general) ....................................... 71 operation ................................................................... 84 overview .................................................................... 71 spi master mode ....................................................... 76 spi slave mode ......................................................... 77 sspbuf ..................................................................... 76 sspsr ....................................................................... 76 multi-master mode ........................................................... 105 o opcode field descriptions ............................................... 159 option_reg register ..................................................... 23 intedg bit ................................................................ 23 ps2:ps0 bits .............................................................. 23 psa bit ....................................................................... 23 rbpu bit .................................................................... 23 t0cs bit ..................................................................... 23 t0se bit ..................................................................... 23 osc1/clki pin .............................................................. 8 , 10 osc2/clko pin ............................................................ 8 , 10 oscillator configuration hs .................................................................... 145 , 149 lp ..................................................................... 145 , 149 rc ............................................................ 145 , 146 , 149 xt ..................................................................... 145 , 149 oscillator selection .......................................................... 143 oscillator start-up timer (ost) ............................... 143 , 148 oscillator, wdt ................................................................ 155 oscillators capacitor selection .................................................. 146 ceramic resonator selection .................................. 145 crystal and ceramic resonators ............................. 145 rc ............................................................................ 146 p package information marking .................................................................... 209 packaging information ..................................................... 209 paging, program memory .................................................. 30 parallel slave port (psp) ....................................... 13 , 48 , 51 associated registers ................................................. 52 re0/rd /an5 pin .................................................. 49 , 51 re1/wr /an6 pin ................................................. 49 , 51 re2/cs /an7 pin .................................................. 49 , 51 select (pspmode bit) ..............................48 , 49 , 50 , 51 parallel slave port requirements (pic16f874a/ 877a only) ....................................... 187 pcl register .......................................................... 19 , 20 , 30 pclath register ................................................... 19 , 20 , 30 pcon register .................................................... 20 , 29 , 149 bor bit ...................................................................... 29 por bit ...................................................................... 29 pic16f87xa product identification system ..................... 231 pickit 1 flash starter kit .................................................. 171 picstart plus development programmer .................... 169 pie1 register ................................................................20 , 25 pie2 register ................................................................20 , 27 pinout descriptions pic16f873a/pic16f876a ........................................... 8 pir1 register ...............................................................19 , 26 pir2 register ...............................................................19 , 28 pop ................................................................................... 30 por. see power-on reset. porta ...........................................................................8 , 10 associated registers ................................................. 43 functions ................................................................... 43 porta register ...................................................19 , 41 trisa register .......................................................... 41 portb ...........................................................................9 , 11 associated registers ................................................. 45 functions ................................................................... 45 portb register ...................................................19 , 44 pull-up enable (rbpu bit) ......................................... 23 rb0/int edge select (intedg bit) .......................... 23 rb0/int pin, external .....................................9 , 11 , 154 rb7:rb4 interrupt-on-change ................................ 154 rb7:rb4 interrupt-on-change enable (rbie bit) ....................................................24 , 154 rb7:rb4 interrupt-on-change flag (rbif bit) ..............................................24 , 44 , 154 trisb register .....................................................21 , 44 portb register ................................................................ 21 portc ...........................................................................9 , 12 associated registers ................................................. 47 functions ................................................................... 47 portc register ...................................................19 , 46 rc3/sck/scl pin ..................................................... 85 rc6/tx/ck pin ........................................................ 112 rc7/rx/dt pin .................................................112 , 113 trisc register ...................................................46 , 111 portd .........................................................................13 , 51 associated registers ................................................. 48 functions ................................................................... 48 parallel slave port (psp) function ............................ 48 portd register ...................................................19 , 48 trisd register .......................................................... 48 porte .............................................................................. 13 analog port pins ...................................................49 , 51 associated registers ................................................. 50 functions ................................................................... 49 input buffer full status (ibf bit) ................................ 50 input buffer overflow (ibov bit) ................................ 50 output buffer full status (obf bit) ........................... 50 porte register ...................................................19 , 49 psp mode select (pspmode bit) ........... 48 , 49 , 50 , 51 re0/rd /an5 pin ..................................................49 , 51 re1/wr /an6 pin ..................................................49 , 51 re2/cs /an7 pin ...................................................49 , 51 trise register .......................................................... 49 postscaler, wdt assignment (psa bit) ................................................ 23 rate select (ps2:ps0 bits) ....................................... 23 power-down mode. see sleep. power-on reset (por) ..................... 143 , 147 , 148 , 149 , 150 por status (por bit) ............................................... 29 power control (pcon) register .............................. 149 power-down (pd bit) ..........................................22 , 147 power-up timer (pwrt) ......................................... 143 time-out (to bit) ................................................22 , 147
? 2003 microchip technology inc. ds39582b-page 225 pic16f87xa power-up timer (pwrt) .................................................. 148 pr2 register ................................................................ 20 , 61 prescaler, timer0 assignment (psa bit) ................................................ 23 rate select (ps2:ps0 bits) ....................................... 23 pro mate ii universal device programmer .................. 169 program counter reset conditions ...................................................... 149 program memory ............................................................... 15 interrupt vector .......................................................... 15 paging ........................................................................ 30 program memory map and stack (pic16f873a/874a) ........................................... 15 program memory map and stack (pic16f876a/877a) ........................................... 15 reset vector .............................................................. 15 program verification ......................................................... 157 programming pin (v pp ) ........................................................ 8 programming, device instructions ................................... 159 psp. see parallel slave port. pulse width modulation. see capture/compare/pwm, pwm mode. push ................................................................................. 30 r ra0/an0 pin .................................................................. 8 , 10 ra1/an1 pin .................................................................. 8 , 10 ra2/an2/v ref -/cv ref pin ............................................ 8 , 10 ra3/an3/v ref + pin ....................................................... 8 , 10 ra4/t0cki/c1out pin .................................................. 8 , 10 ra5/an4/ss /c2out pin ............................................... 8 , 10 ram. see data memory. rb0/int pin ................................................................... 9 , 11 rb1 pin .......................................................................... 9 , 11 rb2 pin .......................................................................... 9 , 11 rb3/pgm pin ................................................................. 9 , 11 rb4 pin .......................................................................... 9 , 11 rb5 pin .......................................................................... 9 , 11 rb6/pgc pin ................................................................. 9 , 11 rb7/pgd pin ................................................................. 9 , 11 rc0/t1oso/t1cki pin ................................................. 9 , 12 rc1/t1osi/ccp2 pin .................................................... 9 , 12 rc2/ccp1 pin ............................................................... 9 , 12 rc3/sck/scl pin ......................................................... 9 , 12 rc4/sdi/sda pin .......................................................... 9 , 12 rc5/sdo pin ................................................................. 9 , 12 rc6/tx/ck pin .............................................................. 9 , 12 rc7/rx/dt pin .............................................................. 9 , 12 rcreg register ................................................................ 19 rcsta register ................................................................. 19 adden bit ............................................................... 112 cren bit .................................................................. 112 ferr bit .................................................................. 112 oerr bit ................................................................. 112 rx9 bit ..................................................................... 112 rx9d bit .................................................................. 112 spen bit .......................................................... 111 , 112 sren bit .................................................................. 112 rd0/psp0 pin .................................................................... 13 rd1/psp1 pin .................................................................... 13 rd2/psp2 pin .................................................................... 13 rd3/psp3 pin .................................................................... 13 rd4/psp4 pin .................................................................... 13 rd5/psp5 pin .................................................................... 13 rd6/psp6 pin .................................................................... 13 rd7/psp7 pin .................................................................... 13 re0/rd /an5 pin ............................................................... 13 re1/wr /an6 pin ............................................................... 13 re2/cs /an7 pin ................................................................ 13 read-modify-write operations ........................................ 159 register file ....................................................................... 16 register file map (pic16f873a/874a) ............................. 18 register file map (pic16f876a/877a) ............................. 17 registers adcon0 (a/d control 0) ......................................... 127 adcon1 (a/d control 1) ......................................... 128 ccp1con/ccp2con (ccp control 1 and ccp control 2) ........................................... 64 cmcon (comparator control) ................................ 135 cvrcon (comparator voltage reference control) .......................................... 141 eecon1 (eeprom control 1) ................................. 34 fsr ........................................................................... 31 intcon ..................................................................... 24 option_reg ......................................................23 , 54 pcon (power control) .............................................. 29 pie1 (peripheral interrupt enable 1) .......................... 25 pie2 (peripheral interrupt enable 2) .......................... 27 pir1 (peripheral interrupt request 1) ....................... 26 pir2 (peripheral interrupt request 2) ....................... 28 rcsta (receive status and control) ..................... 112 special function, summary ....................................... 19 sspcon (mssp control 1, i 2 c mode) ..................... 82 sspcon (mssp control 1, spi mode) ..................... 73 sspcon2 (mssp control 2, i 2 c mode) ................... 83 sspstat (mssp status, i 2 c mode) ........................ 81 sspstat (mssp status, spi mode) ........................ 72 status ........................................................................ 22 t1con (timer1 control) ........................................... 57 t2con (timer2 control) ........................................... 61 trise register .......................................................... 50 txsta (transmit status and control) ..................... 111 reset ........................................................................143 , 147 brown-out reset (bor). see brown-out reset (bor). mclr reset. see mclr . power-on reset (por). see power-on reset (por). reset conditions for pcon register ...................... 149 reset conditions for program counter .................... 149 reset conditions for status register ....................... 149 wdt reset. see watchdog timer (wdt). reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements .......................................................... 184 revision history ............................................................... 219 s sci. see usart. sck ................................................................................... 71 sdi ..................................................................................... 71 sdo ................................................................................... 71 serial clock, sck .............................................................. 71 serial communication interface. see usart. serial data in, sdi ............................................................. 71 serial data out, sdo ........................................................ 71 serial peripheral interface. see spi. slave select synchronization ............................................ 77 slave select, ss ................................................................ 71 sleep ................................................................. 143 , 147 , 156 software simulator (mplab sim) ................................... 168 software simulator (mplab sim30) ............................... 168 spbrg register ................................................................ 20 special features of the cpu ........................................... 143
pic16f87xa ds39582b-page 226 ? 2003 microchip technology inc. special function registers ................................................ 19 special function registers (sfrs) .................................... 19 speed, operating ................................................................. 1 spi mode ..................................................................... 71 , 77 associated registers ................................................. 79 bus mode compatibility ............................................. 79 effects of a reset ....................................................... 79 enabling spi i/o ......................................................... 75 master mode .............................................................. 76 master/slave connection ........................................... 75 serial clock ................................................................ 71 serial data in ............................................................. 71 serial data out ........................................................... 71 slave select ............................................................... 71 slave select synchronization ..................................... 77 sleep operation ......................................................... 79 spi clock ................................................................... 76 typical connection ..................................................... 75 spi mode requirements .................................................. 190 ss ...................................................................................... 71 ssp spi master/slave connection .................................... 75 sspadd register .............................................................. 20 sspbuf register .............................................................. 19 sspcon register .............................................................. 19 sspcon2 register ............................................................ 20 sspif ................................................................................. 26 sspov ............................................................................. 101 sspstat register ............................................................ 20 r/w bit ................................................................. 84 , 85 stack .................................................................................. 30 overflows ................................................................... 30 underflow ................................................................... 30 status register c bit ........................................................................... 22 dc bit ......................................................................... 22 irp bit ........................................................................ 22 pd bit ................................................................. 22 , 147 rp1:rp0 bits ............................................................. 22 to bit ................................................................. 22 , 147 z bit ............................................................................ 22 synchronous master reception associated registers ............................................... 123 synchronous master transmission associated registers ............................................... 122 synchronous serial port interrupt ...................................... 26 synchronous slave reception associated registers ............................................... 125 synchronous slave transmission associated registers ............................................... 125 t t1ckps0 bit ...................................................................... 57 t1ckps1 bit ...................................................................... 57 t1con register ................................................................. 19 t1oscen bit ..................................................................... 57 t1sync bit ........................................................................ 57 t2ckps0 bit ...................................................................... 61 t2ckps1 bit ...................................................................... 61 t2con register ................................................................. 19 t ad ................................................................................... 131 time-out sequence .......................................................... 148 timer0 ................................................................................ 53 associated registers ................................................. 55 clock source edge select (t0se bit) ....................... 23 clock source select (t0cs bit) ................................. 23 external clock ............................................................ 54 interrupt ..................................................................... 53 overflow enable (tmr0ie bit) ................................... 24 overflow flag (tmr0if bit) ................................24 , 154 overflow interrupt .................................................... 154 prescaler .................................................................... 54 t0cki ......................................................................... 54 timer0 and timer1 external clock requirements ........... 185 timer1 ................................................................................ 57 associated registers ................................................. 60 asynchronous counter mode .................................... 59 reading and writing to ...................................... 59 counter operation ..................................................... 58 operation in timer mode ........................................... 58 oscillator .................................................................... 59 capacitor selection ............................................ 59 prescaler .................................................................... 60 resetting of timer1 registers ................................... 60 resetting timer1 using a ccp trigger output ......... 59 synchronized counter mode ..................................... 58 tmr1h ...................................................................... 59 tmr1l ....................................................................... 59 timer2 ................................................................................ 61 associated registers ................................................. 62 output ........................................................................ 62 postscaler .................................................................. 61 prescaler .................................................................... 61 prescaler and postscaler ........................................... 62 timing diagrams a/d conversion ........................................................ 195 acknowledge sequence .......................................... 104 asynchronous master transmission ........................ 116 asynchronous master transmission (back to back) ................................................. 116 asynchronous reception ......................................... 118 asynchronous reception with address byte first ........................................... 120 asynchronous reception with address detect ................................................ 120 baud rate generator with clock arbitration .............. 98 brg reset due to sda arbitration during start condition ................................................. 107 brown-out reset ...................................................... 184 bus collision during a repeated start condition (case 1) .................................. 108 bus collision during repeated start condition (case 2) .................................. 108 bus collision during start condition (scl = 0) ......................................................... 107 bus collision during start condition (sda only) ....................................................... 106 bus collision during stop condition (case 1) ........................................................... 109 bus collision during stop condition (case 2) ........................................................... 109 bus collision for transmit and acknowledge .......... 105 capture/compare/pwm (ccp1 and ccp2) ............ 186 clko and i/o .......................................................... 183 clock synchronization ............................................... 91 external clock .......................................................... 182 first start bit .............................................................. 99
? 2003 microchip technology inc. ds39582b-page 227 pic16f87xa i 2 c bus data ............................................................ 191 i 2 c bus start/stop bits ............................................. 190 i 2 c master mode (reception, 7-bit address) ........... 103 i 2 c master mode (transmission, 7 or 10-bit address) ......................................... 102 i 2 c slave mode (transmission, 10-bit address) ........ 89 i 2 c slave mode (transmission, 7-bit address) .......... 87 i 2 c slave mode with sen = 1 (reception, 10-bit address) ................................................... 93 i 2 c slave mode with sen = 0 (reception, 10-bit address) ................................................... 88 i 2 c slave mode with sen = 0 (reception, 7-bit address) ..................................................... 86 i 2 c slave mode with sen = 1 (reception, 7-bit address) ..................................................... 92 parallel slave port (pic16f874a/877a only) .......... 187 parallel slave port (psp) read ................................. 52 parallel slave port (psp) write ................................. 52 repeat start condition ............................................. 100 reset, watchdog timer, start-up timer and power-up timer ........................................ 184 slave mode general call address sequence (7 or 10-bit address mode) ................................ 94 slave synchronization ............................................... 77 slow rise time (mclr tied to v dd via rc network) .................................................... 152 spi master mode (cke = 0, smp = 0) .................... 188 spi master mode (cke = 1, smp = 1) .................... 188 spi mode (master mode) ........................................... 76 spi mode (slave mode with cke = 0) ....................... 78 spi mode (slave mode with cke = 1) ....................... 78 spi slave mode (cke = 0) ...................................... 189 spi slave mode (cke = 1) ...................................... 189 stop condition receive or transmit mode .............. 104 synchronous reception (master mode, sren) ...................................... 124 synchronous transmission ...................................... 122 synchronous transmission (through txen) .......... 122 time-out sequence on power-up (mclr not tied to v dd ) case 1 .............................................................. 152 case 2 .............................................................. 152 time-out sequence on power-up (mclr tied to v dd via rc network) ................................... 151 timer0 and timer1 external clock .......................... 185 usart synchronous receive (master/slave) .................................................. 193 usart synchronous transmission (master/slave) .................................................. 193 wake-up from sleep via interrupt ............................ 157 timing parameter symbology .......................................... 181 tmr0 register ................................................................... 19 tmr1cs bit ....................................................................... 57 tmr1h register ................................................................ 19 tmr1l register ................................................................. 19 tmr1on bit ....................................................................... 57 tmr2 register ................................................................... 19 tmr2on bit ....................................................................... 61 tmro register .................................................................. 21 toutps0 bit ..................................................................... 61 toutps1 bit ..................................................................... 61 toutps2 bit ..................................................................... 61 toutps3 bit ..................................................................... 61 trisa register .................................................................. 20 trisb register .................................................................. 20 trisc register .................................................................. 20 trisd register .................................................................. 20 trise register .................................................................. 20 ibf bit ........................................................................ 50 ibov bit ..................................................................... 50 obf bit ...................................................................... 50 pspmode bit ........................................... 48 , 49 , 50 , 51 txreg register ................................................................ 19 txsta register ................................................................. 20 brgh bit ................................................................. 111 csrc bit ................................................................. 111 sync bit ................................................................. 111 trmt bit .................................................................. 111 tx9 bit ..................................................................... 111 tx9d bit .................................................................. 111 txen bit .................................................................. 111 u usart ............................................................................. 111 address detect enable (adden bit) ....................... 112 asynchronous mode ................................................ 115 asynchronous receive (9-bit mode) ........................ 119 asynchronous receive with address detect. see asynchronous receive (9-bit mode). asynchronous receiver ........................................... 117 asynchronous reception ......................................... 118 asynchronous transmitter ....................................... 115 baud rate generator (brg) ................................... 113 baud rate formula ......................................... 113 baud rates, asynchronous mode (brgh = 0) .............................................. 114 baud rates, asynchronous mode (brgh = 1) .............................................. 114 high baud rate select (brgh bit) ................. 111 sampling .......................................................... 113 clock source select (csrc bit) .............................. 111 continuous receive enable (cren bit) .................. 112 framing error (ferr bit) ........................................ 112 mode select (sync bit) .......................................... 111 overrun error (oerr bit) ........................................ 112 receive data, 9th bit (rx9d bit) ............................. 112 receive enable, 9-bit (rx9 bit) ............................... 112 serial port enable (spen bit) ..........................111 , 112 single receive enable (sren bit) .......................... 112 synchronous master mode ...................................... 121 synchronous master reception ............................... 123 synchronous master transmission ......................... 121 synchronous slave mode ........................................ 124 synchronous slave reception ................................. 125 synchronous slave transmit ................................... 124 transmit data, 9th bit (tx9d) ................................. 111 transmit enable (txen bit) .................................... 111 transmit enable, 9-bit (tx9 bit) .............................. 111 transmit shift register status (trmt bit) .............. 111 usart synchronous receive requirements ................. 193 v v dd pin ...........................................................................9 , 13 voltage reference specifications .................................... 180 v ss pin ...........................................................................9 , 13
pic16f87xa ds39582b-page 228 ? 2003 microchip technology inc. w wake-up from sleep ................................................ 143 , 156 interrupts .......................................................... 149 , 150 mclr reset ............................................................. 150 wdt reset ............................................................... 150 wake-up using interrupts ................................................ 156 watchdog timer register summary ................................................... 155 watchdog timer (wdt) ........................................... 143 , 155 enable (wdte bit) ................................................... 155 postscaler. see postscaler, wdt. programming considerations ................................... 155 rc oscillator ............................................................ 155 time-out period ........................................................ 155 wdt reset, normal operation ................ 147 , 149 , 150 wdt reset, sleep ................................... 147 , 149 , 150 wcol ................................................................ 99 , 101 , 104 wcol status flag ............................................................. 99 www, on-line support ....................................................... 4
? 2003 microchip technology inc. ds39582b-page 229 pic16f87xa on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
pic16f87xa ds39582b-page 230 ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39582b pic16f87xa 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. ds39582b-page 231 pic16f87xa pic16f87xa product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx xxx pattern package temperature range device device pic16f87xa (1) , pic16f87xat (2) ; v dd range 4.0v to 5.5v pic16lf87xa (1) , pic16lf87xat (2) ; v dd range 2.0v to 5.5v temperature range i = -40 c to +85 c (industrial) package ml = qfn (metal lead frame) pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip l=plcc s = ssop examples: a) pic16f873a-i/p 301 = industrial temp., pdip package, normal v dd limits, qtp pattern #301. b) pic16lf876a-i/so = industrial temp., soic package, extended v dd limits. c) pic16f877a-i/p = industrial temp., pdip package, 10 mhz, normal v dd limits. note 1: f = cmos flash lf = low-power cmos flash 2: t = in tape and reel - soic, plcc, tqfp packages only
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